Coded data generation or conversion – Digital code to digital code converters – To or from variable length codes
Patent
1996-06-20
1998-09-29
Williams, Howard L.
Coded data generation or conversion
Digital code to digital code converters
To or from variable length codes
341 60, H03M 740
Patent
active
058150986
DESCRIPTION:
BRIEF SUMMARY
FIELD OF ART
The present invention relates to a circuit and method for processing variable bit-length codes, and especially to a circuit and method for processing variable bit-length codes which are efficiently, with no blanks, stored in a memory such as compressed data of an image and a sound.
PRIOR ART
One example of such a kind of a variable bit-length code processing circuit is disclosed in, for example, in Japanese Patent Application Laying-open No. 4-245778 laid-open on Sep. 2, 1992. This prior art includes a 1-word shift register (11) which holds input code data, and a 3-word shift register (12) which holds data transferred from the shift register (11) in a bit-parallel fashion, and the data within the shift register (11) is cut-out and transferred by a shift/transfer control portion (30) by the number of the bits capable of filling data blank portions in the shift register (12).
In the above described prior art, since proceeding data which becomes unnecessary is discharged by serially shifting the shift register (12), it is necessary to be provided with shift registers of 4 words in total, and a shift/transfer control which controls shift operations of the shift registers. Although a detail of the shift/transfer control is not disclosed, it is necessary for the shift/transfer control to be provided with a counter for counting the number of the shift times, a control circuit for a shift clock, a transfer control circuit which transfers the data from the shift register (11) to the shift register (12) in a bit-parallel fashion by an arbitrary number of bits, a sequencer and etc., and therefore, a circuit scale becomes large. Furthermore, in order to connect the preceding data to succeeding data in a bit-stream, bits corresponding to blank bits pushed-out by the shift register (11) are shifted by the shift register (12) and written in the shift register (11) bit by bit, and therefore, in the prior art, there was a problem that the number of the processing steps becomes large, and therefore, it takes a long time to withdraw the data.
SUMMARY OF THE INVENTION
Therefore, a principal object of the present invention is to provide a data processing circuit and method capable of rapidly withdrawing a variable bit-length code with a simple circuit.
A variable bit-length code processing circuit in accordance with one aspect of the present invention includes a first 1-word register which holds data applied in a bit-parallel fashion; a second 1-word register which receives the data from the first register in a bit-parallel fashion; a third 1-word register from which a variable bit-length code is withdrawn; a comparison means which compares the number of the valid bits with the number of the remaining bits of the data held in the second register and outputs a first signal at a time that the number of the valid bits is larger than the number of the remaining bits; a first barrel shift means which loads data barrel-shifted from the second register and the third register by the number of the remaining bits to the third register in response to the first signal outputted from the comparison means; a load means which loads the data in the first register to the second register in a bit-parallel fashion in response to the first signal outputted from the comparison means; and a second barrel shift means which loads the data barrel-shifted from the second shift register and the third shift register by the number of the bits equal to a difference between the number of the valid bits and the number of the remaining bits to the second register and the third register after the data in the first register is loaded to the second register by the load means.
Furthermore, in accordance with another aspect of the present invention, a processing method in a variable bit-length code processing circuit which comprises a first 1-word register which holds data applied in a bit-parallel fashion, a second 1-word register which receives the data from the first register in a bit-parallel fashion, and a third 1-word register from which
REFERENCES:
patent: 5140322 (1992-08-01), Sakagami
patent: 5162795 (1992-11-01), Shirota
patent: 5173695 (1992-12-01), Sun et al.
patent: 5245338 (1993-09-01), Sun
patent: 5343195 (1994-08-01), Cooper
patent: 5557271 (1996-09-01), Rim et al.
Takahashi Toyofumi
Tanaka Toshio
Terakawa Hideaki
Creative Design Inc.
Nintendo Co. Ltd.
Williams Howard L.
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