Circuit and method for dynamically generating a clock signal

Details Circuit and method for dynamically generating a clock signal Circuit and method for dynamically generating a clock signal

1992-02-18

1992-10-13

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

328 14, 331 8, 331 14, 331 18, 331116FE, H03L 706, H03L 718

Patent

active

051554518

ABSTRACT:
A clock generator (30) dynamically generates a system clock in response to a high or a low frequency oscillator. An amplified oscillator input is provided to a first input of a multiplexor (62), a divider (56), and a comparator circuit (58, 60). Divider (56) divides an oscillator input frequency to provide a divided input to a second input of multiplexor (62). Comparator circuit (58,60) compares the input frequency with a reference frequency to determine whether the input frequency is high or low. If the input frequency is low, multiplexor (62) is enabled to provide the oscillator input as the system clock. If the input frequency is high, multiplexor (62) provides the divided input as the system clock. Additionally, comparator circuit (58,60) provides a control signal to enable an amplifier (50) to amplify the oscillator input using a high or low gain factor in accordance with the input frequency.

REFERENCES:
patent: 4244043 (1981-01-01), Fujita et al.
patent: 4931748 (1990-06-01), McDermott et al.
"MC68332 User's Manual" published by Motorola, Inc. in 1990, Section 4, pp. 4-4 to 4-53.

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