Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2007-05-29
2007-05-29
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S298000, C327S299000, C327S175000
Reexamination Certificate
active
11267415
ABSTRACT:
A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the first signal and the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal based on the at least one selected version of the second signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.
REFERENCES:
patent: 6094082 (2000-07-01), Gaudet
patent: 6100735 (2000-08-01), Lu
patent: 6121808 (2000-09-01), Gaudet
patent: 6194928 (2001-02-01), Heyne
patent: 6798258 (2004-09-01), Rieven
Hsiang-Hui Chang et al., “A Wide-Range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 40, No. 3, Mar. 2005, pp. 661-670.
Jong-Tae Kwak et al., “A Low Cost High Performance Register-Controlled Digital DLL for 1 Gbps x32 DDR SDRAM,” 2003 Symposium on VLSI Circuits Digest of Technical Papers, pp. 283-284, no month.
Kazuyuki Nakamura et al, “A CMOS 50% Duty Cycle Repeater Using Complementary Phase Blending,” IEEE, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 48-49, no month.
Tatsuya Matano et al., “A 1-Gb/s/pin 512-Mb DDRII SDRAM Using a Digital DLL and a Slew-Rate-Controlled Output Buffer,” IEEE Journal of Solid-State Circuits, vol. 38, No. 5, May 2003, pp. 762-768.
Jang-Jin Nam et al., “An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15%-to-85% for Multi-Phase Applications,” IEICE Trans. Electron, vol. E88-C, No. 4, Apr. 2005, pp. 773-777.
Callahan Timothy P.
Luu An T.
National Semiconductor Corporation
LandOfFree
Circuit and method for digital delay and circuits... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for digital delay and circuits..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for digital delay and circuits... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3727966