Circuit and method for determining overflow in signed division

Details Circuit and method for determining overflow in signed division Circuit and method for determining overflow in signed division

1998-04-08

2000-07-25

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 752

Patent

active

060946695

ABSTRACT:
A circuit and method are provided for dividing a signed numerator by a signed denominator and generating a signal when the division results in overflow condition. The circuit generates a partial remainder using a partial remainder generation circuit, and a partial quotient using a partial quotient generation circuit. The partial remainder is initialized to a first value dependent upon the n most significant bits of the numerator, and the partial quotient is initialized to a first value dependent upon the n least significant bits of the numerator. Second values of the partial remainder and the partial quotient are generated dependent upon the first values of the partial remainder and the partial quotient. An overflow signal is generated if the second value of the partial quotient is equal to zero. The quotient and the remainder are generated dependent upon the second values of the partial remainder and the partial quotient, and the overflow signal is generated dependent upon the quotient.

REFERENCES:
patent: 5016210 (1991-05-01), Sprague et al.
patent: 5574677 (1996-11-01), Cohen
patent: 5615113 (1997-03-01), Matula
patent: 5675528 (1997-10-01), Matula
patent: 5748518 (1998-05-01), Jaggar
patent: 5805489 (1998-09-01), Fernando

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