Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-05-18
2001-07-03
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S362000
Reexamination Certificate
active
06255863
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a technique of determining the level of a differential signal in the field of data communications.
In a communications network, an offsetting comparator is used in tristate level determination of a differential signal, i.e., which of the three conditions of “0”, “1” and “Z” the signal assumes, to see if the potential difference of the differential signal has exceeded an offset voltage.
FIG. 16
illustrates a tristate level determination of a differential signal in compliance with the IEEE 1394 standard. As illustrated in
FIG. 16
, the level of the differential signal is determined as “1” when the potential difference thereof is greater than 165 mV; “0” when the difference is less than −165 mV; and “Z” when the difference is between −165 mV and 165 mV, both inclusive. Such a tristate level determination can be performed by connecting together a pair of comparators with an offset voltage of 165 mV and applying a voltage represented by the differential signal to the inverting input terminal of one of these comparators and to the non-inverting input terminal of the other.
Differential transmission lines are often implemented as a twisted pair of signal lines inside a cable. Thus, when the cable is as long as several meters, the signal lines as the transmission lines might be different in length by as much as several tens centimeters. It is rather probable that the signal lines as the transmission lines are slightly different from each other in capacitance, resistance or impedance depending on the layout of the cable, for example.
Accordingly, if the signal potentials of the differential transmission lines have changed steeply, then the relative potential level standings of the differential signal are sometimes reversed instantaneously.
For example, the signal potentials of differential transmission lines change steeply when the intermediate potential of a differential signal, i.e., a potential level of a common voltage, is used as speed signaling information between two communicating nodes in compliance with the IEEE 1394 standard. Speed is shifted among the three frequencies of 100, 200 and 400 Mbps, for example, depending on the level of the common potential. Thus, when data is transmitted or received, the potential level may change sharply.
FIGS.
17
(
a
) through
17
(
c
) illustrate variations in potential of respective signal lines where the in-phase potentials of differential transmission lines TX and XTX steeply drop at a high speed, e.g., from 2.5 V to 0.5 V in less than 1 ns. FIG.
17
(
a
) illustrates a situation where the transmission lines TX and XTX are of an equal length. FIG.
17
(
b
) illustrates a situation where the transmission line TX is shorter than the transmission line XTX. And FIG.
17
(
c
) illustrates a situation where the transmission line TX is longer than the transmission line XTX.
As shown in FIG.
17
(
a
), where the transmission lines TX and XTX are of an equal length, the potential difference of about 100 to 200 mV is kept as it is even if the potentials have changed steeply. However, if the transmission line TX is shorter than the transmission line XTX, then the signal level standings of these transmission lines TX and XTX are reversed instantaneously while the potentials are dropping as shown in FIG.
17
(
b
). Similarly, if the transmission line TX is longer than the transmission line XTX, the signal level standings of these transmission lines TX and XTX are also reversed instantaneously while the dropped potentials on these lines TX and XTX are rising to their original levels as shown in FIG.
17
(
c
).
A system may have its specifications defined on the supposition that a differential signal keeps its potential difference while the potentials are changed. A logic section of such a system is sometimes so constructed as to sample the output signal of a comparator, which receives the differential signal, as it is responsive to a system clock signal, thereby controlling a state machine. A system with that construction cannot operate stably enough if the potential level standings are reversed as shown in FIGS.
17
(
b
) and
17
(
c
).
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to ensure a stabilized operation for a system that utilizes a determined level of a differential signal even if the intermediate potential of the differential signal changes.
Specifically, an inventive circuit for determining a level of a differential signal includes: a level-determining section, which includes a comparator section receiving the differential signal as input and determines the level of the differential signal by an output of the comparator section; and an intermediate potential monitoring section for sending an information signal, which informs that an intermediate potential of the differential signal will change, to the level-determining section. In response to the information signal received from the intermediate potential monitoring section, the level-determining section determines the level of the differential signal by performing a stabilizing operation such that the level determined is not affected by the change of the intermediate potential.
According to the present invention, if the intermediate potential of the differential signal is expected to change, the level-determining section determines the level of the differential signal by performing a stabilizing operation such that the level determined is not affected by the change of the intermediate potential. Thus, it is possible to avoid an unfavorable situation where a state machine included in a system utilizing the determined level changes into an unexpected state. As a result, the system can operate stably enough.
In one embodiment of the present invention, the level-determining section may perform the stabilizing operation by sampling the output of the comparator section multiple times during a level determination interval and may regard a most frequently sampled value as the level of the differential signal. In this manner, sampled values that have been estimated erroneously just once or a few times can be neglected. Thus, the level determination of the differential signal is not affected by the change of the intermediate potential.
In this particular embodiment, the level-determining section preferably samples the output of the comparator section at a frequency higher than that of a system clock signal for a system that receives the determined level as input.
In another embodiment of the present invention, the level-determining section may perform the stabilizing operation by fixing an input to the comparator section or an output of the comparator section during a level determination interval irrespective of a state of the differential signal. Since the input or output to/from the comparator section is fixed during the level determination interval irrespective of the state of the differential signal, the determined level of the differential signal is not affected by the change of the intermediate potential.
In a specific embodiment, the level-determining section may further include: a switch, provided on the input side of the comparator section, for selectively inputting the differential signal to the comparator section; and a storage section, provided between the comparator section and the switch, for retaining a potential difference represented by the differential signal to be input to the comparator section. During the level determination interval, the switch may be turned OFF such that the differential signal is not input to the comparator section and that the potential difference retained in the storage section is input to the comparator section.
In an alternate embodiment, the level-determining section may further include: a switch, provided on the output side of the comparator section, for selectively passing an output of the comparator section out of the level-determining section; and a storage section, provided on the opposite side of the comparator section with respect
Terada Yutaka
Yamauchi Hiroyuki
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Nguyen Linh
Tran Toan
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