Circuit and method for detecting segment limit errors for code f

Details Circuit and method for detecting segment limit errors for code f Circuit and method for detecting segment limit errors for code f

1994-02-08

1996-10-08

Lane, Jack A.

3954211, G06F 1200

Patent

active

055640303

ABSTRACT:
A segment limit check circuit performs limit checks on fetch addresses generated by a CPU. The circuit and method for performing the fetch limit check are simplified over the prior art by effectively moving the fetch limit check to linear address space. For a microprocessor that uses physical addresses of 32-bits and performs fetches as 16-byte aligned accesses, the circuit of the present invention generates a 33-bit linear address and a 33-bit upper limit value. A comparator compares the upper 29 bits of the linear address with the upper 29-bits of the upper limit value. If a match occurs, the circuit decodes the 4 low-order bits of the upper limit value to determine which of the 16 instruction bytes (if any) fall outside the segment limit.

REFERENCES:
patent: 3814919 (1974-06-01), Repton et al.
patent: 4442484 (1984-04-01), Childs, Jr. et al.
patent: 4851989 (1989-07-01), Kagimasa et al.
patent: 5144551 (1992-09-01), Cepulis
patent: 5274834 (1993-12-01), Kardach et al.
patent: 5321836 (1994-06-01), Crawford et al.
patent: 5418956 (1995-05-01), Willman

Affiliated with

Also associated with

Rating

Circuit and method for detecting segment limit errors for code f does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method for detecting segment limit errors for code f, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for detecting segment limit errors for code f will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-64911