Circuit and method for detecting phase

Details Circuit and method for detecting phase Circuit and method for detecting phase

2007-02-27

2007-02-27

Cleveland, Michael B. (Department: 2892)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S047000

Reexamination Certificate

active

11188952

ABSTRACT:
A circuit for detecting phase includes a first inverter, a second inverter, a differential amplifier, an output load latch and an output latch. The first and second inverters receive an input signal and an inverted input signal to generate first and second differential input signals in response to a clock signal and first and second control signals, respectively, and shut off transmissions of the input signal and the inverted input signal. The differential amplifier differentially amplifies the first and second differential input signals in response to the clock signal to provide first and second differential output signals as the first and second control signals. The output load latch latches the first and second differential output signals to generate the first and second latch output signals. The output latch latches the first and second latch output signals to output a phase detection signal.

REFERENCES:
patent: 2005/0007154 (2005-01-01), Patella et al.
patent: 2006/0055434 (2006-03-01), Tak et al.
patent: 63-11869 (1988-01-01), None
patent: 5-191276 (1993-07-01), None
patent: 2002-111485 (2002-04-01), None
Young-Soo Sohn et al., “A 1.35Gbps Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with 2X Oversampling Phase Detector for Skew Compensation between Clock and Data,” Pohang University of Science and Technology, Pohang, Korea, Sep. 24-26, 2002, IEEE Solid-State Circuits Conference.

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