Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2003-05-16
2004-06-29
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S118000, C341S122000, C330S009000, C330S002000, C327S307000
Reexamination Certificate
active
06756924
ABSTRACT:
TECHNICAL FIELD
The present invention relates to communication systems and, more particularly, circuit for correcting DC offset and signal processing apparatus using thereof.
BACKGROUND OF THE INVENTION
Direct conversion receiver has been developed and applied for many years. In the direct conversion receiver, an input radio signal is down converted to a base band signal without being converted to intermediate frequency (IF) signal. If direct conversion receiver is used, the number of exterior devices can be reduced. Additionally, the amount of digital signal processing is relatively small. Therefore, direct conversion receiver is advantageous because of low cost and being lightness in weight. Further, it is possible to make one chip receiver if direct conversion is used.
FIG. 1
shows a block diagram of a conventional direct conversion receiver.
As shown in
FIG. 1
, the conventional direct conversion receiver comprises a low noise amplifier
101
, a mixer
103
, an amplifier
105
, a filter
107
, and a variable gain amplifier
109
.
Low noise amplifier
101
is a variable gain amplifier. It receives radio signal via antenna to amplify the radio signal while suppressing noise. Mixer
103
mixes the output signal of low noise amplifier
101
with local oscillation signal LO and, thereby, outputs base band signal. Amplifier
105
amplifies the base band signal output from mixer
103
. Filter
107
selects desired signal from the amplified signal. Variable gain amplifier
109
amplifies the output signal of filter
107
while varying the gain of the output signal in order to maintain the required power level of the output signal.
The direct conversion receiver shown in
FIG. 1
has advantages of reduced exterior device and small amount of digital signal processing as described above. However, it suffers from DC offset problem resulting difficulty in being implemented in integrated circuitry.
Primary cause for the DC offset in a direct conversion receiver is the local oscillator leakage. Specifically, leakage of the input radio signal appears at one of the input of the mixer to which local oscillation signal LO is inputted. The leakage components are driven to the mixer
103
together with local oscillation signal LO. Consequently, the input radio signal is mixed with the leakage components of itself at mixer
103
. Similarly, leakage of local oscillation signal LO appears at the input of the mixer to which input radio signal is inputted. The leakage components are driven to the mixer
103
together with the input radio signal. Consequently, local oscillation signal LO is mixed with the leakage components of itself at mixer
103
. The mixing of signals having identical frequency characteristic results in DC offset at the output of mixer
103
. The DC offset resulting from the mixing of signals having identical frequency characteristic is called DC offset by self-mixing. The quantity of DC offset by self-mixing varies continuously in accordance with power level and frequency of input radio signal and local oscillation signal LO.
Secondary cause for DC offset is mismatch of load at output terminal of mixer
103
and duty error of local oscillation signal LO being inputted to mixer
103
.
The other cause for DC offset is mismatch of devices in amplifier and filters. This DC offset varies in accordance with variation of cutoff frequency of filter
107
and gain of variable gain amplifier
109
.
DC offset of direct conversion receiver results from a lot of causes as described above. The amount of DC offset varies continuously in accordance with the variation of frequency of local oscillation signal, input radio signal, gain of amplifiers.
The DC offset problem is one of the major reasons causing deterioration of direct conversion receiver's performance. In this regard, there are a lot of efforts to solve the DC offset problem.
A direct conversion receiver in accordance with one of those efforts is described in U.S. patent application Ser. No. 2002/0094788 published on Jul. 18, 2002 with a title of “Signal processing semiconductor integrated circuit device and wireless communication system” by Norio Hayashi, et al.
FIG. 2
shows a block diagram illustrating the direct conversion receiver described in U.S. patent application Ser. No. 2002/0094788. The direct conversion receiver comprises a dummy low noise amplifier (LNA)
112
B, programmable gain amplifiers PGA
1
-PGA
3
, and low pass filters LPF
1
-LPF
3
. DC offset appearing at the output terminals of amplifiers PGA
1
-PGA
3
is eliminated by using an automatic calibration circuit
117
.
The automatic calibration circuit
117
comprises analog to digital converters
124
A-
124
C, a register REG, digital to analog converters
125
A-
125
C, and a counter
126
. The analog to digital converters
124
A-
124
C convert potential difference of the programmable gain amplifiers PGA
1
-PGA
3
each into digital signals. The digital to analog converters
125
A-
125
C gives input offsets to bring the DC offsets on the outputs thereof into zero to the differential inputs of the corresponding programmable gain amplifiers PGA
1
-PGA
3
on the basis of the comparison results by the analog to digital converters
124
A-
124
C. The counter
126
gives operation timing to each of the digital to analog converters
125
A-
125
C.
According to the direct conversion receiver of
FIG. 2
, the dummy LNA
112
B is activated during the DC offset elimination operation and, then, offsets are given to the differential inputs of the programmable gain amplifiers PGA
1
-PGA
3
through the automatic calibration circuit
117
. Consequently, DC offsets on the output terminals of the amplifiers PGA
1
-PGA
3
are eliminated.
However, according to the direct conversion receiver of
FIG. 2
, DC offsets during only a time for the DC offset elimination operation are eliminated. Therefore, only the DC offsets by leakage of local oscillation signal LO are eliminated, while dynamic DC offsets such as those varying in accordance with the variation of gain of amplifiers. The dynamic DC offsets are amplified by amplifiers PGA
1
-PGA
3
, which results in the deterioration of the receiver's performance. Additionally, since a dummy LNA
112
B was used instead of LNA
112
A to which radio input signal is inputted during the DC offset elimination operation, those DC offsets which vary in dependent on power level variation of the received radio signal are not eliminated.
Other technologies for solving the DC offset problem were introduced by U.S. Pat. Nos. 6,225,848 and 6,114,980.
According to U.S. Pat. Nos. 6,225,848 and 6,114,980, in order to eliminate DC offset on input of a gain stage, a sign bit generator, a binary search stage, and digital to analog converter are used. The gain stage amplifies DC offset between input signals. The amplified DC offset is inputted to the sign bit generator. The sign bit generator outputs either positive or negative sign bit according to the DC offset from the gain stage. The binary search stage determines the direction to which the DC offset may be corrected. Further, according to U.S. Pat. Nos. 6,225,848 and 6,114,980, DC offset is eliminated by forming a feedback loop.
However, in order to eliminate DC offset, it is required that the LNA amplifier at front-end of the receiver should be off. Therefore, DC offset which varies in accordance with power level of radio signal could not be eliminated.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a correction circuit which may eliminate DC offset in real-time base.
Another object of the present invention is to provide a correction circuit which may eliminate DC offset which varies in accordance with the variations of frequency of local oscillation signal and cut off frequency of filters.
Another object of the present invention is to provide a correction circuit which may eliminate dynamic DC offset which varies in accordance with the variations of power level of the signal inputted to a signal processing apparatus.
Another object of the present invention is to provide
Jeong Min-su
Kim Bo-Eun
Kim Bonkee
Lee Junghwan
Lim Jin-kyu
Integrant Technologies Inc.
Mai Lam T.
Shinjyu Global IP Counselors, LLP
Tokar Michael
LandOfFree
Circuit and method for DC offset calibration and signal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for DC offset calibration and signal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for DC offset calibration and signal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3317068