Circuit and method for correcting phase error in a multiplier ci

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Combining of plural signals

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327359, G06F 744

Patent

active

056592639

ABSTRACT:
A circuit and method for reducing a phase error at the output terminal (48) of a multiplier circuit (41) is provided. The phase error arises when first and second input signals having asymmetric signal paths are multiplied in the multiplier circuit (41). A second multiplier circuit (42) multiplies the in-phase and quadrature signals and produces an output signal at an output terminal (49) which contains the phase error but with the opposite polarity as the phase error produced by the first multiplier circuit (41). The signals at the output terminals (48) and (49) are summed in a summing circuit (43) to produce a third output signal in which the phase error is canceled.

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Asad A. Abidi, "Direct-Conversion Radio Transceivers for Digital Communications, IEEE Journal of Solid-State Circuits,", vol. 30, No. 12, Dec. 1995, pp. 1399-1410.

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