Circuit and method for controlling the secondary FET of...

Details Circuit and method for controlling the secondary FET of... Circuit and method for controlling the secondary FET of...

2011-01-25

2011-01-25

Berhane, Adolf (Department: 2838)

Electric power conversion systems

Current conversion

Including d.c.-a.c.-d.c. converter

C363S021130

Reexamination Certificate

active

07876584

ABSTRACT:
A secondary FETsccontrol circuit is disclosed for controlling FETscof transformer coupled synchronous rectified flyback converter (TCSC). The control circuit includes source-drain voltage VSDsense trigger with output VSD-trigger activated upon positive 0-crossing of VSD. Drain-source current IDSsense trigger with output IDS-trigger activated upon positive 0-crossing of IDS. Secondary coil voltage Vsec sense trigger with output Vsec-trigger activated upon sensing negative Vsec. A multi-trigger gate driver (MTGD) has trigger inputs coupled to VSD-trigger, IDS-trigger, Vsec-trigger and drive output driving the FETscgate. The MTGD has logic states of state-I where FETscis turned off and latched, state-II where FETscis turned off but unlatched, state-III where FETscis turned on but unlatched. The MTGD is configured to enter state-III upon VSD-trigger, enter state-I upon IDS-trigger and enter state-IT upon Vsec-trigger. The control circuit thus avoids false triggering of the FETscby numerous undesirable Vsec ringings.

REFERENCES:
patent: 5331533 (1994-07-01), Smith
patent: 6353544 (2002-03-01), Lau
patent: 6778417 (2004-08-01), Itakura et al.
patent: 2001/0026462 (2001-10-01), Tokunaga et al.
patent: 2003/0090914 (2003-05-01), Jansen et al.
patent: 2006/0013022 (2006-01-01), Jitaru

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