Dynamic magnetic information storage or retrieval – General recording or reproducing – Specifics of biasing or erasing
Reexamination Certificate
2000-02-14
2004-08-17
Hudspeth, David (Department: 2651)
Dynamic magnetic information storage or retrieval
General recording or reproducing
Specifics of biasing or erasing
C360S067000
Reexamination Certificate
active
06778345
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The invention relates generally to electronic circuits, and more particularly to a circuit and method for controlling the gain of an amplifier. In one application, a circuit according to the invention provides an initial gain adjustment to a read-signal amplifier in a disk-drive read channel. This initial adjustment allows the amplifier gain-adjust circuitry to more quickly determine and set the proper amplifier gain at the beginning of a data sector. This faster determination and setting allows a reduction in the length of the data-sector preamble, and thus allows an increase in the data-storage density of the disk. Furthermore, because the phase angle between the sample clock and the preamble sinusoid may be unknown at the beginning of the data sector, the circuit can determine the initial gain adjustment independent of this phase angle.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram of a conventional disk-drive read channel
10
, which includes a read path
12
and an gain-control circuit
14
. The read path
12
includes a disk
16
for storing data, a read head
18
for reading data from the disk
16
and for generating a corresponding read signal, a signal-controlled amplifier
20
for amplifying the read signal, an analog-to-digital (A/D) converter
22
for sampling and digitizing the amplified read signal, a finite-impulse-response (FIR) filter
24
for equalizing the digital samples, and a Viterbi detector
26
for recovering the read data from the equalized samples. Although shown having a single A/D converter
22
, the read path
12
may include two or more parallel A/D converters as is well known. The gain-control circuit
14
includes a gain-determination circuit
28
for generating a digital gain-control signal, and a digital-to-analog converter (D/A)
30
for converting the digital gain-control signal into an analog gain-control signal (voltage or current).
FIG. 2
is a diagram of a preamble sinusoid generated by the amplifier
20
of FIG.
1
and having a peak amplitude A. A preamble is a bit pattern that is stored at the beginning of each data sector (not shown) of the disk
16
. This bit pattern is designed such that while the read head
18
reads the preamble, the read signal from the head
18
and the amplified read signal from the amplifier
20
are sinusoids or approximate sinusoids. As discussed below, the read channel
10
uses the preamble to calibrate itself in preparation of the head
18
reading the data that follows the preamble. Because the preamble occupies storage locations that could otherwise store data, one usually desires the preamble to be as short as possible. But if the preamble is too short, then the read channel
10
may calibrate itself improperly, and thus may read the stored data inaccurately. Therefore, the calibration time of the read channel
10
typically dictates the minimum length of the preamble.
Referring to
FIGS. 1 and 2
, the gain-control circuit
14
uses equalized samples of the preamble sinusoid from the FIR filter
24
to calibrate the gain of the amplifier
20
. The Viterbi detector
26
is designed to process samples that are within a predetermined range of values, this range including a predetermined maximum value and a predetermined minimum value. Furthermore, the FIR samples of the preamble-sinusoid's positive and negative peaks respectively correspond to maximum and minimum sample values. Therefore, while the head
18
reads the preamble, the gain-control circuit
14
uses feedback—the amplifier
20
, A/D
22
, FIR
24
and control circuit
14
form a feedback loop—to adjust the gain of the amplifier
20
so that at the output of the FIR
24
, the positive-peak and negative-peak samples equal the predetermined maximum and minimum values, respectively, before the head
18
begins reading data.
Unfortunately, the gain-control circuit
14
often limits the storage density of the disk
16
. To insure that the gain-adjust feedback loop is stable and can finely tune the gain of the amplifier
20
, the circuit
14
typically has a relatively long time constant, i.e., operates relatively slowly. Therefore, the circuit
14
often must process a relatively large number of preamble-peak samples from the FIR
24
before the gain of the amplifier
20
settles to an acceptable level. Consequently, the circuit
14
requires the disk
16
to store a relatively long preamble in each data sector to insure that the amplifier gain settles to an acceptable level before the read head
18
begins reading the data that follows the preamble. Unfortunately, this requirement limits the number of data bits that each data sector can store, and thus limits the total number of data bits that the disk
16
can store.
SUMMARY OF THE INVENTION
In one aspect of the invention, a circuit controls the gain of an amplifier that amplifies an information signal. The circuit includes a buffer that stores two samples of the amplified information signal, and includes a gain-determination circuit coupled to the buffer. The gain-determination circuit generates a gain adjustment that is based on the two samples and that causes the amplifier to shift the amplitude of the amplified information signal to or toward a predetermined amplitude.
Such a circuit can provide an initial, coarse gain adjustment to a read-signal amplifier in a disk-drive read channel. Compared to prior read channels, this initial adjustment promotes faster settling of the amplifier gain at the beginning of a data sector. This faster settling allows the data sector to have a shorter preamble, and thus allows the disk to have a higher data-storage density. Furthermore, because the phase angle between the sample clock and the preamble sinusoid may be unknown at the beginning of the data sector, the circuit can determine the initial gain adjustment independent of this phase angle.
REFERENCES:
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patent: 5034940 (1991-07-01), Saito et al.
patent: 5124967 (1992-06-01), Isaka et al.
patent: 5297184 (1994-03-01), Behrens et al.
patent: 5325394 (1994-06-01), Bruckert
patent: 5343498 (1994-08-01), Toy et al.
patent: 5448424 (1995-09-01), Hirano et al.
patent: 5589877 (1996-12-01), Ikuzawa et al.
patent: 5812025 (1998-09-01), Shimazaki
patent: 6111710 (2000-08-01), Feyh et al.
patent: 6307696 (2001-10-01), Bishop et al.
patent: 01258235 (1989-10-01), None
Hudspeth David
Jorgenson Lisa K.
Kapadia Varsha A.
Santarelli Bryan A.
STMicroelectronics Inc.
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