Circuit and method for controlling loading of write data in...

Details Circuit and method for controlling loading of write data in... Circuit and method for controlling loading of write data in...

2008-12-29

2011-10-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100, C365S233180

Reexamination Certificate

active

08031554

ABSTRACT:
A circuit for controlling the loading of write data in a semiconductor memory device includes a global bus; a data block configured to selectively load data of a predetermined first burst length or data of a second burst length, which is a half of the first burst length, for writing on the global bus in response to a control signal; and a memory bank configured to write the data of the first burst length or the data of the second burst length.

REFERENCES:
patent: 6167487 (2000-12-01), Camacho et al.
patent: 7143258 (2006-11-01), Bae
patent: 2005/0251713 (2005-11-01), Lee
patent: 1020050067448 (2005-07-01), None
patent: 1020080049625 (2008-06-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Dec. 17, 2009.

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