Circuit and method for controlling DRAM column-command address

Details Circuit and method for controlling DRAM column-command address Circuit and method for controlling DRAM column-command address

2011-08-02

2011-08-02

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230010, C365S233100, C365S149000, C365S189020, C365S189150, C365S189160, C365S189050, C365S189120, C365S230060

Reexamination Certificate

active

07990800

ABSTRACT:
The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an input pointer and an output pointer, wherein the output pointer is lagged behind the input pointer by the period number. The FIFO register utilizes the input pointer to store the column-command address, and utilizes the output pointer to output the column-command address.

REFERENCES:
patent: 2004/0039874 (2004-02-01), Johnson
patent: 2005/0270852 (2005-12-01), Dietrich et al.
patent: 2010/0005250 (2010-01-01), Simon et al.

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