Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-07-11
2001-12-25
Mai, Son (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S203000
Reexamination Certificate
active
06333891
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a memory cell generally and, more particularly, to a circuit and method for controlling a wordline and or stabilizing a memory cell.
BACKGROUND OF THE INVENTION
In memory devices, equalization circuits are used to pre-charge bitlines and data lines. Equalization circuits are also used to automatically power down circuitry after a cycle is completed in order to save power (i.e. the wordline may be switched off after a read access if the data is stored in a register).
Traditional uses of equalization circuits allow pre-charge of the data path, and automatic power down after the completion of a cycle. However, during equalization, the memory cell is “fighting” against the equalization circuitry on the bitlines. Such fighting can cause a “crow-bar” current as high as several mA during the equalization time period. Second, should the address change cause a new wordline to be selected before equalization has pulled the bitlines to a high enough level, the contents of the newly selected cell can be overwritten. Such a condition is known as read disturb or write disturb (depending on the cycle that causes the problem). The use of a register in the data path so that the wordlines can be turned off after a read cycle, creates an additional critical timing relationship. The register must be clocked during the time when correct data is available from the memory cell no matter what the relationship of the address signals. This can be a difficult condition to satisfy over all process corners, voltages, and temperatures.
SUMMARY OF THE INVENTION
The present invention concerns a circuit and method for controlling a wordline and/or stabilizing memory cells comprising a first circuit and a second circuit. The first circuit may be configured to generate a control signal in response to a select signal and an equalization signal. The second circuit may be configured to generate a local wordline signal in response to (i) the control signal and (ii) a global wordline signal. The output signal may be presented to one or more memory cells of a memory array.
The objects, features and advantages of the present invention include providing an apparatus that may (i) simplify address timing relative to bitline pre-charge, (ii) use an equalization signal to disable the address path, (iii) force all local wordlines off during equalization, (iv) prevent read and/or write disturb during bitline equalization, (v) reduce power consumption due to “crow-bar” current from the bitline pre-charge circuitry and the memory cells, (vi) reduce DC power consumed by allowing the bitlines to split to full CMOS levels, and/or (vii) be implemented in asynchronous and/or synchronous devices.
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Adamek Peter
Landry Greg J.
Cypress Semiconductor Corp.
Mai Son
Maiorana P.C. Christopher P.
Miller Robert M
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