Circuit and method for controlling a synchronous rectifier...

Electric power conversion systems – Current conversion – With condition responsive means to control the output...

Reexamination Certificate

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C363S127000, C363S053000, C323S239000

Reexamination Certificate

active

06191964

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to power systems and, more particularly, to a control circuit for operating a power rectifier in both a bidirectional and unidirectional mode of operation as a function of a characteristic of the power system.
BACKGROUND OF THE INVENTION
Increased power density is a continuing goal of modern power supply design. High power density is particularly crucial in applications wherein the allocated space for the power supply relative to the power output is restricted. In addition to being highly compact, the power supply must also be efficient to limit heat-creating power dissipation. Illustrative applications for a high density power supply include an off-line power supply used to power a laptop computer or a power supply module for a telecommunication system employing an Integrated Services Digital Network (“ISDN”).
Bridge-type converters are particularly suitable for such applications, since they may be designed to operate resonantly. Resonance is an operational mode that permits both high power density and efficiency. One example of a bridge-type converter is a half-bridge converter as disclosed in U.S. Pat. No. 5,274,543 to Loftus, issued on Dec. 28, 1993, entitled “Zero-Voltage Switching Power Converter with Lossless Synchronous Rectifier Gate Drive” and incorporated herein by reference. Loftus converter operates as a forward converter and includes a bridge circuit comprising two power switching transistors to drive a primary transformer.
Loftus discloses a drive arrangement and operative scheme for driving the power transistors, thereby limiting the dissipation losses within the power switching transistors. The drive circuitry drives the power switching transistors with unequal duty cycles having a conducting duration such that the sum of the conduction intervals substantially equals the combined switching period of the power transistors. The conducting intervals are separated by very short dead time intervals controlled by the differing turn-on and turn-off times of the power switching transistor. The short interval between alternate conductions of the power switching transistors is sufficient in duration to allow zero voltage turn-on of the power switching transistors but short enough in duration to minimize power loss and conducted noise.
Another area of concern in a power supply is an additional loss of efficiency realized through the power dissipated in the rectifier circuit of the converter. While a Schottky diode rectifier is approximately 80% efficient, a metal oxide semiconductor field effect transistor (“MOSFET”) synchronous rectifier is nearly 90% efficient.
While synchronous rectification is a relatively old concept, it has failed to gain widespread acceptance because of the unavailability of cost-effective, low R
DS(on)
rectifier devices (those having a small static drain-source resistance while forward-biased). Prior practical implementations have required designers to couple many higher R
DS(on)
devices in parallel to arrive at a suitably low overall R
DS(on)
Recent advances in high cell density MOSFET technology, however, have made available MOSFET devices with very low (<10 milliohms) R
DS(on)
in cost-effective, commercial packages. As a result, synchronous rectification has recently regained widespread interest; companies are beginning to introduce power converters using synchronous rectification into the marketplace.
The normal operating mode for converters operating with forced load-sharing is for each converter to provide an equal portion of the total load current. A control terminal of the converters are coupled together in a star connection, thereby providing the necessary feedback to equalize the load currents actively.
However, it is well known in the industry that synchronous rectifier circuits are capable of processing power bidirectionally, both from the input to the output, and from the output back to the input (of course, provided a voltage or current source externally drives the output). Bidirectional current flow can provide some significant advantages, perhaps the most common of which is elimination of the so-called critical current phenomenon found in buck-derived converters. The bidirectional current flow characteristic allows inductor current in the synchronous rectifier circuit to flow continuously, thereby avoiding a sluggish reaction to a load or transient on the output of the converter circuit.
However, for converters connected in parallel with forced load-sharing, this bi-directional power flow characteristic can result in an undesirable (and possibly damaging) operating mode wherein one converter drives the output of another. With one or more converters operating in this reverse power processing mode, the overall power system can be circulating large amounts of current while actually delivering very little current to the load. This results in high power dissipation during lighter load conditions. Also, the system transient response could be detrimentally affected as the converters transition from the reverse power processing mode to a forward power processing mode.
Parallel (forced load-sharing) circuitry in each converter, responsible for driving the rectifier devices, may not be able to prevent this mode of operation, as the parallel circuit is specifically designed to be effective over a limited range. See U.S. Pat. No. 5,036,452 to Loftus, issued on Jul. 30, 1991, entitled “Current Sharing Control with Limited Output Voltage Range for Paralleled Power Converters,” and incorporated herein by reference, for a discussion of load sharing between power circuits connected in parallel to a common load. Therefore, it is beneficial to provide a circuit that prevents reverse power flow in converters configured for parallel operation.
The aforementioned predicament of reverse power flow in converters for parallel operation is the subject of two articles. These articles introduce a circuit wherein the synchronous rectifier control voltage is modified to prevent reverse power flow. The circuits are generally designed either to prevent reverse power flow at converter start-up or to address “hot plug-in” problems encountered when substituting individual converters in a functioning power system.
In the first article, “A Highly Efficient, Low-Profile 300-W Power Pack for Telecommunications Systems,” APEC 1994 Proceeding, pp. 786-792, by N. Murakami, I. Yumoto, T. Yachi and K. Maki, a resonant reset forward converter with a novel synchronous rectifier drive circuit is disclosed. The circuit comprises a pair of switches to disable the gate drive of one synchronous field effect transistor (“FET”) based on switch current. Another synchronous FET uses an output inductor to generate the drive voltage, and can be configured off when the inductor current goes discontinuous. The idea is to detect when the converter goes into discontinuous conduction mode, and to use this information to disable the synchronous rectifiers, thus preventing a catastrophic failure. The described circuit, which is designed for parallel operation, uses droop regulation to achieve load sharing, rather than active load sharing using a parallel pin connection. The circuit, thus, turns one of the FETs off based on switch current, and the other FET off based on a discontinuous current condition.
While the Murakami et al. circuit attempts to solve the proposed problem it is limited for the following reasons. First, the circuit as described is only compatible with a self-synchronized drive scheme. Moreover, the circuit as described apparently only has a problem when a converter-falls below critical inductor current. Both the transformer secondary voltage and the inductor voltage can collapse to zero during discontinuous conduction mode. The output voltage supplied by the paralleled modules could then energize the gates of the synchronous FETS, thus turning them on at the wrong time. Stated another way, the resonant reset topology forces a finite dead time in the gate drive of one synchronous FET, allo

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