Circuit and method for conditioning flash memory array

Details Circuit and method for conditioning flash memory array Circuit and method for conditioning flash memory array

1999-06-24

2000-12-26

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518524, 36518529, G11C 1604

Patent

active

061669628

ABSTRACT:
A novel cell conditioning mechanism is employed to equalize charge discharge characteristics of flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, and leaves other cells relatively unaffected so that the fast bits are adjusted to have threshold voltages closer to those of the other cells in an array. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

REFERENCES:
patent: 5343434 (1994-08-01), Noguchi
patent: 5428568 (1995-06-01), Kobayashi et al.
patent: 5594689 (1997-01-01), Kato
patent: 5901089 (1999-05-01), Korsh et al.
patent: 5930174 (1999-07-01), Chen et al.
patent: 5991195 (1999-11-01), Nobukata

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