Amplifiers – With periodic switching input-output
Reexamination Certificate
2000-04-27
2002-07-30
Mottola, Steven J. (Department: 2817)
Amplifiers
With periodic switching input-output
C330S253000
Reexamination Certificate
active
06426674
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to operational amplifiers, and more specifically to a circuit and method for compensating the offset voltage at the output of an operational amplifier.
2. Description of Related Art
A conventional operational amplifier is an analog (i.e., linear) circuit which can amplify voltages with a very high gain (e.g., 10,000 or more). It produces at its output a voltage which is proportional to the potential difference presented at its two inputs, which are known as the inverting and non-inverting inputs. The amplified voltage output is delivered at low impedance, so it is possible to drive relatively high loads without incurring significant stability losses. Conversely, the inputs exhibit a very high impedance, so as to allow weak signals to be amplified. Because of these advantageous characteristics, operational amplifiers are very widely used as basic elements in electronic circuits, such as drive, filtering, sampling, signal conversion (e.g., between analog and digital), and measurement circuits. They are also used as a virtual ground (i.e., to form a node in a circuit that exhibits a zero or fixed voltage without current consumption).
Operational amplifiers are generally constructed in the form of integrated circuits. In a typical application, several separate operational amplifiers can be integrated on a common substrate with numerous other circuit elements, which can be both analog and digital. For instance, a very large scale integration (VLSI) integrated circuit can include several tens of operational amplifiers, digital-to-analog converters, memories, a microprocessor, and the like to form a specific functional unit such as a control loop. An operational amplifier can be constructed with either bipolar transistors or field effect transistors, such as MOS transistors. There now exist operational amplifiers made using CMOS technology which can operate at very low voltages (e.g., on the order of 2V). Amplifiers made using CMOS technology can be integrated on a common substrate with digital CMOS circuits.
FIG. 1
shows a simplified circuit diagram of a conventional CMOS operational amplifier. This operational amplifier is based on a two-stage architecture having a differential input stage and a gain stage. In this amplifier, the gain stage also constitutes the operational amplifier's output stage. The active elements of the differential input stage are formed by two NMOS transistors Q
1
and Q
2
, which constitute a differential pair. The control gates of transistors Q
1
and Q
2
are connected to the inverting input EI and the non-inverting input ENI, respectively.
The differential input stage is connected to a load in the form of a current source that is formed by two PMOS transistors Q
3
and Q
4
, which are connected to form a current mirror. The gain stage includes a PMOS transistor Q
5
and its active load formed by transistors Q
7
, Q
8
, and Q
9
. The operation of the current sources is established by an input or a fixed reference current EIref. Conventionally, a compensation for the characteristics between the open loop and closed loop modes is obtained by a pole sharing capacitor C. Since the amplifier is given a unitary gain, this capacitor C is coupled between the output S and the gain stage input.
In principle, because an operational amplifier amplifies a difference in voltage between its two inputs EI and ENI, the voltage VO at the output S should be zero when these inputs are at the same potential (for example, by being connected together). However, in practice, an operational amplifier exhibits a spurious output voltage known as the offset voltage when there is no potential difference between the two inputs EI and ENI. This offset voltage is due to an imbalance between the characteristics of the amplifier's respective inputs EI and ENI. Thus, the offset voltage is a component of the output signal which distorts the operation of the operational amplifier relative to its theoretical characteristics.
In the CMOS technology circuits currently being used for digital applications by virtue of their low current consumption, it is often necessary to bring together on the same substrate analog circuits such as differential amplifiers with purely digital circuit elements. At present, the use of operational amplifiers in logic circuits, especially in CMOS technology, is limited by non-uniformities in the transistor characteristics, which are linked to fabrication processes. Although tolerable with logic circuits which operate in a binary mode, these non-uniformities give rise to relatively large offset voltages (e.g., on the order of 5 to 10 mV in the case of operational amplifiers).
Techniques exist for calibrating an operational amplifier so as to reduce the offset voltage. Such zero-setting techniques consist in biasing one of the inputs EI or ENI of the amplifier (or more often an intermediate stage downstream of these inputs) with a fixed compensation voltage. This compensation voltage is set so as to re-balance the amplifier's inputs EI and ENI so that the output voltage V
0
is substantially equal to zero when the inputs EI and ENI are at the same potential. A first conventional operational amplifier zero-setting technique consists in periodically alternating the amplifier's operating mode between a measurement phase and a normal operating mode phase. During the measurement phase, the two inputs EI and ENI of the operational amplifier are connected together so as to bring them to the same potential, and the amplifier's offset voltage S is detected (e.g., by a sample-and-hold circuit). This offset voltage is used to produce a compensation voltage applied to a compensation input of the amplifier.
FIG. 2
shows an exemplary circuit for resetting to zero the offset voltage by using a sample-and-hold circuit. A switch
2
is connected to one of the inputs (ENI) of the operational amplifier
1
to connect that input selectively either to an external input voltage Vin in the normal operating mode (position P
1
), or to the amplifier's other input (EI) during the measurement phase (position P
2
). A reference voltage source VS
1
just before the EI input of the amplifier
1
serves to set the two inputs ENI and EI to the same potential during the measurement phase. During the measurement phase, the switch
2
is positioned at position P
2
to disconnect the ENI input from its external input signal Vin and to set the amplifier's two inputs EI and ENI to the voltage Vref of voltage source VS
1
. The voltage at the amplifier's output S then corresponds to the offset voltage. This voltage is zeroed by applying a compensation voltage at an intermediate input N of the amplifier
1
.
For this purpose, a feedback circuit is provided between the output S and the intermediate input N of the amplifier
1
. In this exemplary amplifier, the feedback circuit includes a sample-and-hold circuit
4
whose input receives the output signal of the amplifier
1
via a buffer amplifier
6
and whose output is connected to the intermediate input N. The feedback circuit
4
and
6
serves to provide the right correction voltage at the intermediate input N by successive samplings. When this correction voltage is obtained, the switch
2
is set to position P
1
to allow the amplifier to operate in the normal mode. However, the operational amplifier cannot fulfil its normal function of amplifying the signal Vin during this measurement phase.
The sample-and-hold technique can be replaced by a digital approach as shown in the exemplary amplifier of FIG.
3
. The connections and operation at the inputs ENI and EI of the amplifier
1
are identical to those of the amplifier of FIG.
2
. However, the sample-and-hold circuit
4
, which is essentially analog in nature, is replaced by a digital register
8
and a digital-to-analog converter
1
0
. During the measurement phase (with the switch
2
at position P
2
), the digital register
8
successively records at each cycle of a clock Cl
Bongini Stephen
Fleit Kain Gibbons Gutman & Bongini P.L.
Jorgenson Lisa K.
Mottola Steven J.
STMicroelectronics S.A.
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