Circuit and method for cancelling nonlinearity error associated

Details Circuit and method for cancelling nonlinearity error associated Circuit and method for cancelling nonlinearity error associated

1992-07-01

1993-06-22

Pellinen, A. D.

Coded data generation or conversion

Converter compensation

341120, H03M 106

Patent

active

052219267

ABSTRACT:
A circuit (10) and method for minimizing nonlinearity errors in an oversampled data converter (40) resulting from errors in the intended values of components (42-49) of the converter (40). An adder section (11) is used to add a digital input sample to a previously existing sum generated from an immediately preceding digital input sample. A resulting sum is converter from binary code to thermometer code by an encoder (20). Combinatorial logic (24) is used to provide control signals for controlling switching of the components in a manner which both converts the nonlinearity error to a noise error and frequency shifts the noise error out of a frequency passband of the converter to higher frequencies where the error is subsequently filtered.

REFERENCES:
patent: 4894656 (1990-01-01), Hwang et al.
patent: 4999625 (1991-03-01), Thompson
IEEE Proc. CICC, "A 16-Bit 4'th Order Noise-Shaping D/A Converter", Carley et al., pp. 21.7.1-21.7.4, 1988.
A master's thesis paper entitled "Multi-Bit .SIGMA..DELTA. Analog-to-Digital Converters with Nonlinearity Correction Using Dynamic Barrel Shifting" by Y. Sakina, May 1990, Univ. of Calif. at Berkeley, Abstract pg. and pp. 23-26.

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