Wave transmission lines and networks – Dissipating terminations for long lines – Fluid-cooling
Reexamination Certificate
2002-10-16
2004-07-27
Tan, Vibol (Department: 2819)
Wave transmission lines and networks
Dissipating terminations for long lines
Fluid-cooling
C333S213000, C324S601000, C326S030000, C326S032000, C327S108000, C330S260000, C365S189120
Reexamination Certificate
active
06768393
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of priority of Korean Patent Application No. 01-83343 filed on Dec. 22, 2001, the disclosures of which are hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to bus termination in a memory system, and more particularly, to a circuit and method for calibrating resistors to have the same resistance as that of an external resistor irrespective of changes in process, voltage, or temperature.
2. Discussion of Related Art
In general, a bus of a memory system is terminated using stub bus terminated logic (SSTL) or active termination. The active termination is also called ‘on-chip termination’ and terminates a bus of a memory system using an active termination resistor in a chip (hereinafter, referred to as ‘termination resistor’). The active termination is advantageous in that it has better signal integrity and facilitates operation of the memory system at higher data rate than SSTL.
The key point of the active termination depends on how precisely the termination resistor can be calibrated for termination resistance. In the prior art, an analog control voltage is used as a control signal to calibrate the termination resistor. However, since the control voltage is sensitive to noise, it is difficult to precisely calibrate the termination resistor with the control voltage, and further, the signal transfer characteristics of a bus may deteriorate.
Conventionally, the active termination is performed using two chips in common (hereinafter, referred to as ‘×2’) or four chips in common (hereinafter, referred to as ‘×4’). However, in both cases, at least another circuit is further required for calibrating the termination resistor (as compared to the active termination using one chip). Thus, in the conventional active terminations, the overhead of the circuit layout as well as power consumption increases markedly.
SUMMARY OF THE INVENTION
A circuit and method is provided for calibrating an active termination resistor irrespective of changes in process, voltage or temperature, and a memory device including such a circuit.
An embodiment of the present invention provides a method of reducing power consumption and the overhead of the circuit layout, and a memory device for performing the method.
There is also provided a method of calibrating an active termination resistor, the method including the steps of (a) calibrating a first variable resistor to have the same resistance as that of an external resistor, and at the same time calibrating a second variable resistor to have the same resistance as that of the first variable resistor; and (b) calibrating the active termination resistor to have the same resistance as that of the external resistor.
Here, step (a) includes calibrating the first variable resistor to have the same resistance as that of the external resistor in response to a first control code, and at the same time calibrating the second variable resistor to have the same resistance as that of the first variable resistor in response to a second control code.
The first control code is generated to correspond to a comparison value in resistance of the first variable resistor with the external resistor, and the second control code is generated to correspond to a comparison value in resistance of the first variable resistor with the second variable resistor
During step (a), the resistance of the first variable resistor and the resistance of the second variable resistor increase or decrease at the same time.
There is also provided a circuit for calibrating an active termination resistor to have the same resistance as that of an external resistor, the circuit including a first control circuit for comparing voltage at a first node, to which the external resistor is connected, with a reference voltage, and for outputting a first control code for controlling a first variable resistor that supplies electric current to the first node; and a second control circuit for comparing voltage at a second node, to which a second variable resistor is connected, with voltage at the first node, and for outputting a second control code for controlling a dummy variable resistor that supplies electric current to the second node and is the same as the first variable resistor, wherein the resistance of the first variable resistor and the resistance of the dummy variable resistor are calibrated in response to the first control code, and at the same time the second variable resistor is calibrated to have the same resistance as that of the external resistor in response to the second control code, and the active termination resistor is calibrated to have the same resistance as that of the external resistor in response to the first control code and/or the second control code.
According to another aspect of the invention, there is provided a circuit for calibrating an active termination resistor to have the same resistance as that of an external resistor, the circuit including a first node to which the external resistor and a first variable resistor are connected; a first control code generation circuit for comparing voltage at the first node with a reference voltage, and for outputting a first control code corresponding to a comparison result; a second node to which a dummy variable resistor, which is the same as the first variable resistor, and a second variable resistor are connected; and a second control code generation circuit for comparing voltage at the first node with voltage at the second node, and for outputting a second control code corresponding to the comparison result, wherein the first variable resistor and the dummy variable resistor are calibrated in response to the first control code, and at the same time the second variable resistor is calibrated to have the same resistance as that of the external resistor in response to the second control code, and the active termination resistor is calibrated to have the same resistance as that of the external resistor in response to the first control code and/or the second control code.
Preferably, the resistance of the first variable resistor and the resistance of the second variable resistor increase or decrease at the same time. Also, preferably, voltage at the first node is generated in response to electric current flowing through the first variable resistor, and voltage at the second node is generated in response to electric current flowing through the dummy variable resistor.
There is further provided a memory device including a calibrating circuit for outputting first and second control codes; a shifter block for multiplexing the first and second control codes in response to a selection signal, and for outputting control codes controlling an active termination resistor; and variable resistor units for calibrating the active termination resistor to have the same resistance as that of an external resistor connected to the calibrating circuit in response to the control codes.
Here, the calibrating circuit includes a first node connected to the external resistor and a first variable resistor; a first control code generation circuit for comparing voltage at the first node and a reference voltage, and for outputting the first control code corresponding to a comparison result; a second node connected to a dummy variable resistor, which is the same as the first variable resistor, and a second variable resistor; and a second control code generation circuit for comparing voltage at the first node with voltage at the second node, and for outputting the second control code corresponding to the comparison result, wherein the first variable resistor and the dummy variable resistor are calibrated to have the same resistance as that of the external resistor in response to the first control code, and at the same time the second variable resistor is calibrated to have the same resistance as that of the external resistor in response to the second control code.
REFERENCES:
paten
F. Chau & Associates LLC
Tan Vibol
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