Circuit and method for avoiding soft errors in storage devices

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing

Reexamination Certificate

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Details

C716S105000, C716S106000, C716S110000, C716S111000, C716S112000, C716S119000, C716S122000, C716S124000

Reexamination Certificate

active

08042071

ABSTRACT:
A storage element within a circuit design is identified. The storage element is replaced with both a first storage cell and a second storage cell. The second storage cell operates as a redundant storage cell to the first storage cell. An output of the first storage cell is connected to a first input of a comparator and an output of the second storage cell is connected to a second input of the comparator. The comparator provides an error indicator. Placement of the first storage cell, the second storage cell, the comparator, and one or more intervening cells is determined. The one or more intervening cells are placed between the first storage cell and the second storage cell. An integrated circuit is created using the comparator, the first storage cell, the second storage cell, the one or more intervening cells, and the determined placement.

REFERENCES:
patent: 6825691 (2004-11-01), Chu et al.
patent: 6826090 (2004-11-01), Chu et al.
patent: 6882201 (2005-04-01), Koch, II et al.
patent: 6930527 (2005-08-01), Cabanas-Holmen et al.
patent: 7215581 (2007-05-01), Lotz et al.
patent: 2004/0205385 (2004-10-01), Smith
patent: 2006/0227596 (2006-10-01), Thayer

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