Electrical pulse counters – pulse dividers – or shift registers: c – Shift register
Reexamination Certificate
1998-05-01
2001-08-14
Lam, Tuan T. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Shift register
C377S069000
Reexamination Certificate
active
06275558
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a circuit for generating an M-sequence code (Maximum Length Code) which is used as a spread code such in a frequency spread communication (Spread Spectrum Communication), and particularly to the circuit for shifting the M-sequence code with an arbitrary bit. An M-sequence is a kind of PN (Pseudorandom Noise), which can be easily generated by a shift register comprising D-type flip-flops
1
-
6
having a feedback circuit using an exclusive OR circuit
7
as shown in
FIG. 9
, for example. Accordingly, the M-sequence code is often used as a spread code in a spread spectrum communication.
In the spread spectrum communication, it is necessary for a reception side to generate an inverse spread code which synchronizes and coincides with the spread code, so that it is necessary to have a synchronization by arbitrarily shifting the M-sequence which is used in spreading.
There has been known a conventional circuit disclosed in JP-A-8-181679 (1996), which is one of conventional methods for arbitrarily shifting the M-sequence. The conventional technology is shown in FIG.
10
.
In
FIG. 10
, entire data of the M-sequence or PN-sequence are stored in a ROM look-up table
54
. An address added to the ROM
54
includes a value of which an N-bit binary counter
53
counts a system clock signal
56
, and a value of which an adder
52
adds an offset signal
55
which is held in a register
51
based on an external designation. Since the address increases one by one at every one count of the clock signal
56
by the counter
53
, the ROM
54
outputs in the order a PN-sequence
57
stored therein.
Further, the offset signal
55
is written in the register
51
to increase the address with its amount so as to output a shift output signal as the PN-sequence
57
, thereby enabling to arbitrarily shift the PN-sequence.
By the way, in the conventional example described above, it is necessary to store entire of the M-sequence or PN-sequence in the ROM, and it is no problem if a stage number of the M-sequence is small.
However, in the case of the M-sequence having 42 stages such in
FIG. 11
, for example, a cycle is 2
42
−1 bit which corresponds to about 4000 Gbit. There has not been a ROM for holding such large data, which is impractical idea at the present time.
Further,
FIG. 11
is a circuit diagram showing a circuit for generating a long code as a kind of a spread code, which is used in the IS95 system of CDMA (Code Division Multiple Access) in U.S.A. The circuit uses an M-sequence of a forty-second stage, and comprises registers
601
-
642
, adders
643
-
648
, AND gate circuits
649
-
690
, a modulo adder
691
, thereby obtaining a long code
693
of which a bit is random shifted corresponding to a value of a mask code
692
which is inputted in the AND gate circuits
649
-
690
.
The mask code
692
is used as a cipher key, and it is necessary that mask codes are the same as each other in the transmission side and the reception side.
Accordingly, there has been no original purpose to shift the M-sequence with an arbitrary number of bits by using the mask code. Therefore, it is necessary that a mask code corresponding to a shift amount thereof is previously obtained and stored for shifting the M-sequence. Accordingly, it is difficult to instantaneously shift it with an arbitrary number of bits.
SUMMARY OF THE INVENTION
The objective of the present invention is to solve the above-mentioned tasks.
Moreover, the objective of the invention is to provide a technology for arbitrarily shifting an M-sequence, the circuit capable of generating the M-sequence, which is shifted with an arbitrary number of bits by a small circuit scale.
The objective of the present invention is achieved by a circuit for arbitrarily shifting an M-sequence, which comprises shift registers of N-stage and for generating an M-sequence, a plurality of two to the several power bits shift inserting circuits connected in series between an output N-bit of each stage of the shift register and the final output N-bit.
Furthermore, each of the two to the several power bit shift inserting circuits, comprises a two to several power bit shifting circuit for shifting an N-bit input signal with two to several power bits, and a data selector for outputting after changing over the N-bit input signal and an N-bit signal outputted from the two to several power bit shifting circuit corresponding to an external control signal, so as to output an N-bit output signal.
Moreover, the two to several power bit shift inserting circuit has an exponent of the power of two, which is an integral number of N from 0 to N−1.
Still furthermore, a circuit for arbitrarily shifting an M-sequence necessarily has only a two to several power bit shift inserting circuit which has a specific integral number from 0 to N−1 as an exponent of the power of two.
REFERENCES:
patent: 6061417 (2000-05-01), Kelem
patent: 6181733 (2001-01-01), Shinde
patent: 129444 (1989-06-01), None
patent: 131815 (1989-06-01), None
patent: 8181679 (1996-07-01), None
Lam Tuan T.
NEC Corporation
Ostrolenk Faber Gerb & Soffen, LLP
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