Multiplex communications – Wide area network – Packet switching
Patent
1993-12-14
1995-08-15
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
H04J 306
Patent
active
054426367
ABSTRACT:
A frame aligner circuit for aligning a plurality of information packet signals received within a maximum starting time variation interval consists of a plurality of frame detectors, stretch circuits and variable delay circuits which are controlled by a synchronization signal generator and a delay control circuit. The delay control circuit in one embodiment of the present invention delays each information packet signal for a duration of time defined by the start of the information packet signal and an interval of time following the start of a last received information packet signals. In this manner, each information packet signal is delayed a corresponding period of time to align the plurality of information packet signals with respect to one another.
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"General Aspects of Digital Transmission Systems; Terminal Equipment," CCITT Blue Book, vol. III, Nov. 1988, pp. 107-174.
AT&T Corp.
Olms Douglas W.
Patel Ajit
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