Patent
1996-02-23
1997-01-21
Treat, William M.
395411, 395412, 395415, 395800, G06F 938, G06F 942
Patent
active
055967353
ABSTRACT:
In a processor having a protected mode of operation in which a computer memory associated with the processor contains global and local descriptor tables addressed by a combination of a base address and an index, the processor having (i) global and local base address registers alternatively to provide the base address and (ii) a selector for containing the index and a table indicator (TI) bit indicating which of the global and local base address registers is to provide the base address, the processor requiring a time to derive the index and a value of the TI bit and a further time to combine the index and the base address, a base address register predicting circuit to predict, and a method of predicting, which of the global and local base address registers is to provide the base address without having to wait for the processor to derive the value of the TI bit. The circuit includes (i) TI bit predicting circuitry to generate a predicted value of the TI bit as a function of a prior value of the TI bit, and (ii) register access circuitry to access one of the global and local base address registers as a function of the predicted value of the TI bit.
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Garibay, Jr. Raul A.
Hervin Mark W.
Cyrix Corporation
Maxin John L.
Najjar Saleh
Treat William M.
Viger Andrew S.
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