Electric power conversion systems – Current conversion – With condition responsive means to control the output...
Reexamination Certificate
2000-05-08
2001-04-17
Nguyen, Matthew (Department: 2838)
Electric power conversion systems
Current conversion
With condition responsive means to control the output...
C363S021040
Reexamination Certificate
active
06219262
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to voltage regulator circuits. More specifically, the present invention is directed to pulse-width modulated current mode controllers in switching regulators which commonly utilize leading edge blanking circuitry.
2. Background
Conventional current mode control circuits result in unique waveforms which can interfere with proper regulation of the output voltage in switching power supplies. A typical current mode control circuit commonly used in switching power supplies is represented by the block diagram circuit of FIG.
1
A. In general, sensed current through an inductive load coupled to a power transistor is used for current mode control and cycle-by-cycle current limiting. The current mode control circuit has a voltage feedback loop
100
and a current-sense feedback loop
102
which work together to provide a regulated output voltage at V
out
104
. However, a gate charge current pulse (I
charge
)
142
alters the leading edge of a current-sense waveform causing erroneous response in the peak current sensing feedback control circuitry and interferes with the proper regulation of the output voltage V
out
104
.
In the example current mode control circuit of
FIG. 1A
, the voltage and current-sense feedback loops
100
,
102
control the pulse width of the gate drive voltage pulse V
g
106
which opens and closes the power transistor main switch
108
. The main switch
108
is typically a MOSFET switch that, in conjunction with inductor
103
, facilitates the transfer of energy from the voltage input V
cc
110
to the voltage output V
out
104
by opening and closing in response to the drive pulse V
g
106
. The width of each drive pulse V
g
106
is regulated by feedback through the voltage and current-sense feedback loops
100
,
102
and determines the length of time during each clock cycle that the main switch
108
remains closed in order to build up energy in the inductor L
103
. The longer the switch
108
is closed, the larger the transferred energy, resulting in a larger voltage output V
out
104
. Conversely, a shorter conduction interval of switch
108
results in a lower voltage output V
out
104
. The drive pulse V
g
106
is generated by a constant-frequency clock
112
driving a latch
114
. The output voltage V
out
104
is thus regulated by the constant-frequency, pulse-width modulated voltage pulse V
g
106
.
In operation, the voltage and current-sense feedback loops
100
,
102
modulate the width of the drive pulse V
g
106
by continually monitoring the output voltage V
out
104
and sensing the current flowing through the main switch
108
. In the example current mode control circuit of
FIG. 1A
, 5 volts has been chosen as a typical value for V
out
104
. Resistors R
1
116
and R
2
118
make up a voltage divider which divides down V
out
104
to provide a V
error
120
voltage which is continually monitored within the voltage feedback loop
100
. A voltage reference V
ref
122
is set such that V
error
120
is equal to V
ref
122
when V
out
104
is properly regulated to 5 volts. A typical value for V
ref
122
is 1.25 volts, and thus the resistors R
1
116
and R
2
118
are selected to provide a value of 1.25 volts at V
error
120
for a properly regulated V
out
104
value of 5 volts. Any change in voltage at V
out
104
results in a corresponding change in V
error
120
. The voltage difference between V
error
120
and V
ref
122
is then amplified by the error amplifier
124
, resulting in an adjustment of the error amplifier
124
output voltage level V
ea
126
. During each clock cycle, a current-sense comparator
128
compares V
ea
126
with the current-sense voltage V
s
130
, which is the voltage across a current-sense resistor R
s
132
that rises as current flows through the closed main switch
108
. The current-sense voltage V
s
130
tracks the linearly increasing current through inductor L
103
, and thus the energy being transferred from the voltage input V
cc
110
to the voltage output V
out
104
, during each clock cycle as the main switch
108
is in a closed position due to the gate drive pulse V
g
106
. During each clock cycle, the gate drive pulse V
g
106
keeps the main switch
108
closed until the current-sense voltage V
s
130
rises to the level of V
ea
126
, at which point the current-sense comparator
128
resets the R-S flip-flop
114
which terminates the gate drive pulse V
g
106
and opens the main switch
108
until the next clock cycle begins. Thus, the current-sense comparator
128
uses the monitored output voltage V
out
104
and the sensed current through inductor L
103
to modulate the width of the drive pulse V
g
106
and regulate V
out
104
.
The operation of the current mode control circuit of
FIG. 1A
is more readily understood with reference to the clock pulse
112
, the gate drive pulse V
g
106
and the voltage V
s
130
waveforms as shown in FIG.
1
B. The gate drive pulse V
g
106
begins with each clock pulse
112
and acts to close the main switch
108
, causing a linear rise in current through inductor L
103
and a corresponding rise in the current-sense voltage V
s
130
across the current-sense resistor R
s
132
. When V
s
130
rises to the level pre-set by error amplifier
124
output voltage V
ea
126
, the current-sense comparator
128
resets the R-S flip-flop
114
, terminating the gate drive pulse V
g
106
which opens the main switch
108
and causes resistor R
s
132
to pull V
s
130
to ground until the next clock cycle begins.
A change in the error amplifier
124
output voltage V
ea
126
, as shown for example by V
ea2
136
in
FIG. 1B
, is the result of the voltage feedback loop
100
of
FIG. 1A
responding to a drop in the output voltage V
out
104
. As is apparent from the V
s2
131
waveform of
FIG. 1B
, a drop in the output voltage V
out
104
results in a widening of the gate drive pulse V
g
106
holding the main switch
108
closed, since V
s2
131
must rise to a higher level in order to reach V
ea2
136
and cause comparator
128
to reset the R-S flip-flop
114
. Thus, the voltage and current-sense feedback loops
100
,
102
work to correct the drop in output voltage V
out
104
by holding the main switch
108
closed for a longer period of time during each clock cycle
112
so that more energy is transferred from the voltage input V
cc
110
to the voltage output V
out
104
.
In addition to illustrating the operation of a typical current mode control circuit in a switching power supply,
FIGS. 1A & 1B
also illustrate the fundamental problem associated with using the current-sense voltage V
s
130
waveform to control the complex current mode control circuitry. The current-sense voltage V
s
130
waveform is not usable in its natural form to control the current mode control circuit because of the leading edge spike
138
which is apparent in the V
s
130
waveform of
FIGS. 1B & 2B
. The partial circuit of FIG.
2
A and accompanying waveforms of
FIG. 2B
illustrate how the gate drive pulse V
g
106
is differentiated by a series connection of the the gate-source capacitance C
gs
140
of the MOSFET switch
108
and the current-sense resistor R
s
132
resulting in the leading edge spike
138
. It is apparent from the waveforms of
FIG. 2B
that the leading edge spike
138
of the current-sense voltage V
s
130
reaches its peak value at the same time that the gate charge current pulse I
charge
142
(I
charge
path also illustrated in
FIG. 1A
) reaches its peak through the current-sense resistor R
s
132
during the MOSFET switch
108
turn-on transition. Although several factors influence the leading edge spike
138
such as bias conditions in the driver circuitry
144
, reverse recovery characteristics of the diode D
1
146
, transformer parasitics and the Miller effect, the main source of the leading edge spike
138
is the gate-source capacitance C
gs
140
of the MOSFET switch
108
. The value of the leading edge spike
138
in the current-sense voltage V
s
Nguyen Matthew
Ritchie David B.
Semtech Corporation
Thelen Reid & Priest LLP
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