Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
2001-08-21
2002-10-08
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S202000, C438S340000, C438S364000, C438S238000, C438S258000, C438S345000
Reexamination Certificate
active
06461926
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits and, in particular, to a circuit and method for a memory cell using reverse base current effect.
BACKGROUND
Modern electronic systems typically include a data storage device such as a dynamic random access memory (DRAM), static random access memory (SRAM) or other conventional memory device. The memory device stores data in vast arrays of memory cells. Each cell conventionally stores a single bit of data (a logical “1” or a logical “0”) and can be individually accessed or addressed.
Electronic systems, e.g., computers, conventionally store data during operation in the memory device. As these systems become more sophisticated, they require more and more memory capacity to keep pace with the increasing complexity of software based applications that run on the systems. Thus, as the technology relating to memory devices has evolved, designers have tried to increase the density of memory cells in the memory device by decreasing the size of the memory cells. This allows a larger number of memory cells to be fabricated without substantially increasing the size of the semiconductor wafer that houses the memory device.
Static random access memory or “SRAM” is one type of memory device that is used with electronic systems, e.g., computers. Conventionally, an SRAM device includes an array of addressable memory cells. Each cell includes a four transistor flip-flop and access transistors that are coupled to input/output nodes of the flip-flop. Data is written to the memory cell by applying a high or low logic level to one of the input/output nodes of the flip-flop through one of the access transistors. When the logic level is removed from the access transistor, the flip-flop retains this logic level at the input/output node. Data is read out from the flip-flop by turning on the access transistor.
Memory devices are fabricated using photolithographic techniques that allow semiconductor and other materials to be manipulated to form integrated circuits as is known in the art. These photolithographic techniques essentially use light that is focussed through lenses to define patterns in the materials with microscopic dimensions. The equipment and techniques that are used to implement this photolithography provide a limit for the size of the circuits that can be formed with the materials. Essentially, at some point, the lithography cannot create a fine enough image with sufficient clarity to decrease the size of the elements of the circuit. In other words, there is a minimum dimension that can be achieved through conventional photolithography. This minimum dimension is referred to as the “critical dimension” (CD) or minimum feature size (F) of the photolithographic process.
The minimum feature size imposes one constraint on the size of conventional cells in an SRAM device. Conventionally, SRAM cells have used a surface area on a substrate that is approximately equal to 120 feature squares (F
2
). Some researchers have used vertical transistors to reduce the size of the memory cells to as small as 32 feature squares.
In order to keep up with the demands for higher capacity memory devices, designers have dabbled with changing the mechanism of cell operation in an SRAM cell to produce SRAM cells of smaller size. For example, some researchers have used the mechanism of complementary metal-on-semiconductor (CMOS) latchup. This mechanism is a negative differential resistance phenomenon which provides two current states at the same voltage. Unfortunately, in one of these states, the SRAM cell can draw a large current. This can result in a high power consumption for large arrays of SRAM cells.
Other researchers have attempted to use the negative resistance characteristic of tunnel diode mechanism to redesign the conventional SRAM cell. The tunnel diode device has two voltage levels for the same current. However, the tunnel diodes in such a structure may require heavy doping not normally associated with conventional CMOS fabrication techniques.
Some researchers have proposed an SRAM cell structure that is based on the reverse base current effect of a bipolar junction transistor. This is a two transistor cell with a bipolar junction storage transistor and a field effect transistor acting as a switch to pass voltages in and out of the cell. Essentially, this structure is capable of storing data because, when a sufficient voltage is maintained between the collector and the emitter of the bipolar junction transistor, the base current of the transistor is zero for two distinct voltages applied to its base. Typically, the bipolar junction transistor does not conduct any base current in this configuration when the base voltage is either zero volts or 0.6 volts. This allows the transistor to store two different logic states; both at essentially no current. The voltage stored on the base of the bipolar junction transistor is read using techniques similar to conventional DRAM devices.
Unfortunately, the researchers have not contemplated how to reduce the size of these cells so as to increase the density of cells of an SRAM array even further.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an SRAM cell with reduced surface area.
SUMMARY OF THE INVENTION
The above mentioned problems with memory cells and other problems are addressed by the present invention and will be understood by reading and studying the following specification. An improved memory cell is described which occupies a reduced surface area on the substrate by using a single mask to define the location of wordlines, ground buses and isolation regions with widths at the minimum dimension (F). This single mask allows a reduction in the size of the memory cell to approximately six feature squares by self-aligning a vertical bipolar junction transistor with the minimum dimension isolation region.
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Brock II Paul E
Lee Eddie
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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