Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
1999-03-18
2001-01-30
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S291000, C327S299000
Reexamination Certificate
active
06181182
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to clocking architecture, and, more particularly, to a circuit and method for a high gain, low input capacitance inverting clock buffer.
BACKGROUND OF THE INVENTION
In many integrated circuit devices, it is desirable to provide a system clock, or reference clock, signal to a number of devices within the integrated circuit package. It is also desirable to uniformly delay the reference clock signal such that the clock signal is supplied to the appropriate devices simultaneously. Typically, the clock signal is delayed by the combination of the clock buffers and a clock routing tree, or grid. A known clock buffer is illustrated in FIG.
1
.
FIG. 1
is a schematic diagram of a known clock buffer
11
. A clock input signal CKIN is supplied on connection
17
to one input of NAND gate
12
and one input of NOR gate
14
. NAND gate
12
provides output X on connection
21
and NOR gate
14
provides output Y on connection
19
. Outputs X and Y are the inverse of clock input signal on connection
17
. NAND gate
12
provides input to transistor
22
and NOR gate
14
provides input to transistor
24
. The output of transistors
22
and
24
in the form of a signal Z is provided over connection
26
to both inverter
27
and inverter
29
. Inverter
29
supplies signal F over connection
18
to an input of NOR gate
14
and inverter
27
provides the inverse clock signal output NCK on connection
31
as feedback to NAND gate
12
via connection
16
and as input to inverter
28
, the output of which is supplied as input to inverters
27
and
29
.
The operation of clock buffer
11
is as follows.
Case 1 (transition)
0) Initial conditions: Z←1F←0 NCK←0 CKIN←0
1) X←1 Y←1
2) U
1
←off D
1
←on
3) Z←0
4) F←1NCK←1
5) Y←0
6) D
1
←off; go to case 3
Case 2 (transition)
0) Initial conditions: Z←0 F←1 NCK←1 CKIN←1
1) X←0 Y←0
2) U
1
on D
1
off
3) Z←1
4) F←0 NCK←0
5) X←1
6) U
1
←off, go to case 4
Case
3
(stable)
0) Initial conditions: Z←0 F←1 NCK←1 CKIN←0
1) X←1 Y←0
2) U
1
←off D
1
←off
3) upon CKIN←1, go to case 2
Case 4 (stable)
0) initial conditions: Z←1 F←0 NCK←0 CKIN←1
1) X←1 Y←0
2) U
1
←off DI
1 off
3) upon CKIN←0, go to case 1
The circuit can start in the initial state of any of cases 1-4.
A drawback with the type of clock buffer described above is that it has a high input capacitance, thereby requiring many buffers, or a single large buffer, to drive the input. This condition consumes valuable space on the integrated circuit assembly.
Therefore, it would be desirable to have a clock buffer that is capable of high gain, and that has a lower input capacitance, and reduces the amount of space consumed in an integrated circuit.
SUMMARY OF THE INVENTION
The invention provides an inverting clock buffer having high gain and low input capacitance and method for generating a high drive strength clock signal in a high gain, low input capacitance clock buffer.
In architecture, the present invention may be conceptualized as an inverting clock buffer having high gain and low input capacitance, comprising: first logic configured to receive an input clock signal and supply a delayed version of the input clock signal; and a first transistor and a second transistor configured to receive the delayed input clock signal, the first transistor and the second transistor driving an output, the output being an inverse of the input clock signal.
The present invention may also be conceptualized as a method for generating a high drive strength clock signal in a high gain, low input capacitance clock buffer, the method comprising the steps of: supplying a delayed input clock input signal to a first transistor and a second transistor, the transistors configured to alternatively switch an output signal between a logic low value and a logic high value; and operating the first transistor when the second transistor is in a stable state and operating the second transistor when the first transistor is in a stable state.
The invention has numerous advantages, a few of which are delineated, hereafter, as merely examples.
An advantage of the invention is that it significantly reduces the input capacitance of a clock buffer.
Another advantage of the invention is that it significantly reduces the amount of space on an integrated circuit consumed by an inverting clock buffer.
Another advantage of the invention is that it significantly reduces the amount of average and instantaneous power consumed by an inverting clock buffer.
Another advantage of the invention is that it is simple in design and easily implemented on a mass scale for commercial production.
Other features and advantages of the invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. These additional features and advantages are intended to be included herein within the scope of the present invention.
REFERENCES:
patent: 4283639 (1981-08-01), Roesleer
patent: 4692637 (1987-09-01), Shoji
patent: 4950920 (1990-08-01), Hara et al.
patent: 5672991 (1997-09-01), Thoma et al.
patent: 5867043 (1999-02-01), Kim
patent: 5874845 (1999-02-01), Hynes
patent: 355118226 (1980-09-01), None
patent: 401117516 (1989-05-01), None
Krzyzkowski Richard A.
Nuber Paul D.
Stotz Dan
Agilent Technologies
Lam Tuan T.
LandOfFree
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