Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-11
2003-09-16
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S189090
Reexamination Certificate
active
06621737
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a circuit and an associated method for the erasure or programming of a memory cell. The invention is especially useful for electrically programmable and erasable, non-volatile type memories, such as EEPROMS, flash EPROMS and other similar memories.
BACKGROUND OF THE INVENTION
A main component of a memory cell of these memories is a floating-gate storage transistor comprising a drain, a source, a control gate and a floating gate that stores information. The programming of a memory cell is usually carried out in two steps: an erasing step followed by a writing step.
To carry out a memory cell erasure step, a high voltage is applied to the control gate of the storage transistor and zero voltage is applied to the drain and source. Thus, the potential difference between the control gate and the drain of the storage transistor sets up an electrical field across the control gate and the drain. This causes electrons to migrate from the source and the drain to the floating gate, and therefore, results in the discharging of the floating gate.
Conversely, to carry out a memory cell write step, zero voltage is applied to the control gate of the storage transistor and a high voltage is applied the drain. The source is taken to a floating potential. The potential difference across the control gate and the drain of the storage transistor creates an electrical field with opposite polarity. This causes electrons to migrate in the reverse direction, from the floating gate of the storage transistor to its drain.
Thus, to carry out a memory cell write or erasure step, a high erasure or programming voltage of about 15 to 20 V needs to be available. This voltage is applied to either electrode of the storage transistor of the memory cell, depending on the operation to be performed.
However, the oxide layer between the floating gate and the drain of the storage transistor is thin and brittle. Thus, when the voltage applied to the electrodes of the storage transistor is greater than what is called the tunnel voltage, it should not vary sharply. Indeed, any sharp variation in the voltage leads to the creation of high current between the floating gate and the drain or source of the transistor. An excessive current would make the oxide layer brittle and could even damage it.
It may be recalled that the tunnel voltage is the minimum voltage needed for a charge to travel by the tunnel effect through the oxide layer, between the floating gate and the drain of a floating gate transistor. Typically, the value of the tunnel voltage is in the range of 10 V.
To obtain a voltage that varies gradually and slowly, the classic method is to use an erasure or programming circuit, a known example of which is shown in a diagrammatic view in
FIG. 1
a
. This circuit
100
has a voltage step-up circuit
101
, a voltage ramp production circuit
102
and a shaping circuit
103
. All three are powered with a low power supply voltage VDD (not shown in
FIG. 1
a
) in the range 2 to 3 V for 0.25 &mgr;m technology.
The voltage step-up circuit
101
is, for example, a charge pump type of circuit. It produces a high voltage HIV of about 15 to 20 V from the low power supply voltage VDD. The circuit
102
produces a ramp voltage RAMP from the high voltage HIV. This ramp voltage RAMP has, for example, the shape shown by the unbroken line in
FIG. 1
b
. The ramp voltage RAMP includes a rising phase
110
during which the voltage RAMP rises continuously up to its maximum value VMAX, which is, for example, equal to the high voltage HIV. This is followed by a voltage plateau
111
during which the voltage RAMP is constant, that is, equal to the value VMAX. There is a voltage drop
112
after the voltage plateau
111
.
The ramp generation circuit
102
conventionally comprises a circuit for the charging and discharging of a power capacitor. The circuit is powered by a current source that gives a reference current IREF. The rising phase
110
of the voltage RAMP is obtained by charging a capacitor with a charging current ICH. The voltage plateau
111
for its part is obtained by the discharging of this capacitor with a discharging current IDECH.
The charging and/or discharging current used are most usually, but not necessarily, proportional to the reference current IREF and are constant. They are usually different from one another. The rising phase
110
may be lengthier or shorter than the voltage plateau
111
, depending on the value of the current ICH with respect to the value of the current IDECH. The rising phase
110
and the voltage plateau
111
have a total duration TRAMP that corresponds to the duration of an erasure or programming operation.
An appropriate choice of the capacitance of the capacitor as well as the reference current IREF optimizes the slope of the rising phase
110
including the total duration TRAMP. This choice is generally a compromise based on the following criteria. When the voltage applied to the electrodes of the storage transistor is higher than the tunnel voltage, it must not vary sharply. For this purpose, the slope of the rising phase
110
must not cross a boundary value.
The total duration TRAMP must be sufficiently long for the voltage TRAMP to have the time to reach its maximum value VMAX. The voltage plateau must last long enough to ensure the full completion of an erasure or programming step, and the total duration TRAMP must be as small as possible.
The shaping circuit
103
receives the voltage RAMP and produces a high erasure or programming voltage VPP that is applied to either electrode of the memory cell (not shown in
FIG. 1
a
), depending on whether the memory cell is to be erased or programmed. The high erasure or programming voltage VPP has, for example, the shape shown by the dashes in
FIG. 1
b.
This shape includes a first voltage plateau
115
, during which the voltage VPP is equal to the low supply voltage VDD, and a rising phase
116
followed by a second voltage plateau
117
. The voltage VPP is equal to the voltage RAMP, minus a drop in voltage VTN in a transistor. The shape also includes a drop in voltage
118
, during which the voltage VPP falls back to the voltage VDD.
The voltage VPP thus follows the variations in the voltage RAMP, minus a drop in voltage VTN of about 2 V, which corresponds approximately to the conduction threshold voltage of an N-type transistor. During a programming of a memory cell, zero voltage is applied to a control gate of a floating-gate transistor, a voltage equal to VPP is applied to the drain of the transistor, and its source is left at a floating potential. The current ID flowing between the drain and the source of the transistor has, in this case, the shape shown in
FIG. 1
c.
The current ID is zero when the voltage VPP is rising, and is smaller than the tunnel voltage. Then it rises sharply (ref.
120
) from zero up to a maximum value IDMAX when VPP crosses the tunnel voltage. The value IDMAX is reached when VPP reaches its maximum value VPPMAX. The current ID then falls again (ref.
121
) throughout the duration of the plateau
117
, then it drops sharply to zero (ref.
122
) when the voltage VPP drops (
118
) to its minimum value VDD. During an erasure of the memory cell, the current flowing between the drain and the source has a similar shape. It flows simply in the reverse direction to that of its flow in the case of a programming operation.
The erasure time TER (or programming time TWR) of the memories is in the range of about 3 ms. The memory
7
erasure or programming time is thus relatively long. This may be particularly damaging in certain cases. For example, during the manufacture of the memories, all the cells of the memory are especially subjected to an endurance test. This endurance test generally includes the successive execution of several erasure and/or programming operations (about 500 such operations) to verify whether the cells have been properly manufactured, and if they meet the required specifications, especially in terms of durability.
This endurance test is only one among a
Bertrand Bertrand
Chehadi Mohamad
Naura David
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Lam David
STMicroelectronics SA
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