Incremental printing of symbolic information – Ink jet – Controller
Reexamination Certificate
1999-08-16
2001-08-28
Barlow, John (Department: 2853)
Incremental printing of symbolic information
Ink jet
Controller
C347S059000
Reexamination Certificate
active
06280011
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to electronic circuits and ink jet printers, and more particularly to ink jet printer assemblies with multiple print heads.
BACKGROUND AND SUMMARY OF THE INVENTION
Ink jet printers employ print heads that reciprocate over a media sheet and expel droplets through an array of nozzles, onto the sheet to generate a printed image or pattern. To provide faster printer speeds without compromising print quality, print heads have been developed with longer nozzle arrays to provide a wider print swath. This has required proportionately larger print head chips, with attendant concerns of manufacturablility, wafer edge losses, and the fact that a single defect requires rejection of a more valuable component. In addition, certain applications may benefit from wider print swaths than can be practically provided by a single print head chip. Accordingly, assemblies with multiple print head chips can provide a wider print swath.
Multi-chip print head assemblies and other multi-chip assemblies may employ Low Voltage Differential Signaling (LVDS) to transmit high frequency data signals to the chips, such as on a clock line shared by all chips operating in concert. LVDS operates under the ANSI/TIA/EIA-644-1995 standard and the IEEE 1596.7-1996 standard, and provides a low-noise means for transmitting very high frequency data. This is particularly important as printer resolution and speed is increased, requiring a higher data rate for a given printed area. A receiver on each chip has a pair of input lines across which a terminating resistor is connected. The signal to the receiver is transmitted in the form of small current values that reverse direction to indicate changes in the data state. This generates a corresponding changing small voltage across the terminating resistor (from small positive to small negative values), in response to which the receiver generates an output signal at conventional logic voltage levels to other circuitry on the chip.
For multi chip assemblies sharing a parallel input line pair, the terminating resistance may be provided by a single resistor shared by all chips, or by a resistor at each chip. A single resistor will have the standard resistance, and multiple resistors will each have a resistance equal to the product of the standard resistor and the number of resistors. Typically, a component resistor may be installed across the input line pair, typically at the most remote component. However, the addition of one or more such components increases the size, complexity and cost of the assembly.
The resistor or resistors also may be provided internally to the chip(s). To eliminate the resistor component, a resistor may be provided across the line pair internally to the chips. If only one chip is provided with the standard-value terminating resistor and the others are without resistors, two types of chips must be inventoried, and kept segregated for manufacturing purposes. If identical chips each having a high value resistor (standard resistance x number of chips) are used, there are two disadvantages. First, the use of the large resistors of multiplied size requires area on the chip that increases chip size and cost. Second, a different chip design (with appropriately multiplied resistor value) is required for each assembly design using a different number of chips.
The present invention overcomes the limitations of the prior art by providing an integrated circuit chip with a low voltage differential signaling receiver (LVDS). The receiver has first and second input lines, and an output line. The first input line is connected to a first input node on the chip, and the second input line connected via a termination resistor on the chip to a second input node on the chip. The second input line is connected to a third input node on the chip. The chip may be installed on a substrate with one or more identical chips, with the first nodes of each chip connected to a first conductor on the substrate, and a second conductor on the substrate connected to the third node of each chip. A second node on one of the chips is connected to the first conductor to involve the resistor.
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Beck Jeffery S.
Ghozeil Adam L
Schloeman Dennis J.
Barlow John
Dudding Alfred
Hewlett--Packard Company
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