Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-09-19
2002-04-09
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06369599
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to electronic devices, and more specifically, to a circuit for dynamically configuring bond-pad connections for different operational modes of an integrated circuit.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, one or more dies
2
are formed in a conventional manner on a wafer
4
, which is formed from a semiconductor material such as silicon. The dies
2
are integrated circuits or devices that have been formed, but have not been detached from the wafer
4
. For clarity, only one row of dies
2
is shown, but will be understood that generally multiple rows of dies
2
are formed to substantially fill the surface of the wafer
4
. During a wafer test procedure, conventional apparatus (not shown) electrically tests the dies
2
. The testing apparatus includes probes that contact selected ones of the bond pads (not shown) of the dies
2
.
A limitation associated with such a wafer test procedure is that each bond pad that will receive a signal from the testing apparatus often must be placed only along the sides
8
of the dies
2
in order to perform simultaneously testing of multiple dies
2
. Because the dies
2
are placed relatively close together along their sides
6
to maximize the area of the wafer
4
occupied by the dies
2
, the bond pads that are located along the adjacent sides
6
are often inaccessible to the probes of the testing apparatus, particularly when all of the dies
2
on the wafer
4
are tested simultaneously. That is, the probes of the testing apparatus can often only contact the accessible bond pads that are located along the other sides
8
of the dies
2
. (The dies
2
are typically formed in the wafer
4
such that there is sufficient clearance for the test probes to access the sides
8
of each of the dies
2
.) Requiring the bond pads that are used during the wafer test procedure to be located only along the sides
8
may cause inefficient and complex circuit layouts on and increase the areas of the dies
2
.
Referring to
FIG. 2
, which shows a top view of a die
2
of
FIG. 1
, a known solution to this limitation is discussed. For clarity, the wafer
4
and the remaining dies
2
of
FIG. 1
are omitted from FIG.
2
. The die
2
includes accessible test pads
10
and accessible bond pads
14
, which are located along accessible sides
8
, and inaccessible pads
12
, which are located along inaccessible sides
6
. For clarity,
FIG. 2
shows only two test pads
10
a
and
10
b
, two inaccessible bond pads
12
a
and
12
b
, and two accessible bond pads
14
a
and
14
b
, it being understood that the die
2
may include more or less of each of these pads. Each test pad
10
is electrically coupled to circuitry (not shown) that is coupled to a corresponding pad
12
and that is to receive a signal from the testing apparatus during a wafer test procedure. Thus, by physically accessing test pads
10
, the testing apparatus can electrically access the circuitry that is coupled to the inaccessible pads
12
. Once the test is complete, however, the pads
10
typically serve no further purpose.
A limitation of this known solution is that the length of the accessible sides
8
must be sufficient to accommodate the required number of the pads
14
and the test pads
10
. Thus, the test pads
10
often increase the length of the sides
8
, and thus often increase the area of the die
2
.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, an integrated circuit is provided. The integrated device includes a circuit that is coupled to first and second bond pads and first and second conductive paths of the integrated device. The circuit receives a map signal that has a first value during a first operational mode of the integrated device and a second value during a second operational mode of the integrated device. In response to the first value, the circuit couples the first pad to the second conductive path. In response to the second value, the circuit couples the first pad to the first conductive path and the second pad to the second conductive path.
An advantage provided by one aspect of the invention is a reduction in the number of test pads required in a die.
An advantage provided by another aspect of the invention is a reduction in the area of a die.
REFERENCES:
patent: 4336495 (1982-06-01), Hapke
patent: 4339710 (1982-07-01), Hapke
patent: 4357703 (1982-11-01), Van Brunt
patent: 4398146 (1983-08-01), Draheim et al.
patent: 4698588 (1987-10-01), Hwang et al.
patent: 4733168 (1988-03-01), Blankenship et al.
patent: 4743841 (1988-05-01), Takeuchi
patent: 4980889 (1990-12-01), DeGuise et al.
patent: 5107208 (1992-04-01), Lee
patent: 5153509 (1992-10-01), Dalrymple
patent: 5301143 (1994-04-01), Ohri et al.
patent: 5303180 (1994-04-01), McAdams
patent: 5469075 (1995-11-01), Oke et al.
Wright Jeffrey P.
Zheng Hua
Dorsey & Whitney LLP
Karlsen Ernest
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