Cryptography – Key management – Having particular key generator
Patent
1989-02-02
1990-11-20
Cangialosi, Salvatore
Cryptography
Key management
Having particular key generator
380 50, H04K 100
Patent
active
049724819
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to a ciphering device for serially transmitted information, comprising an input for a sequence of bits to be ciphered, an output for the ciphered bit sequence, and a mixing unit connected between the input and the output, said mixing unit being adapted to receive both the bit sequence to be ciphered and a sequence of code bits for ciphering said bit sequence, and, by a mixing operation, to generate the ciphered bit sequence, and a code unit adapted to generate code bits and comprising a shift register into which bits from the ciphered bit sequence are shifted, and a memory containing code bits and addressed with bits from the shift register.
The invention also relates to a deciphering device which is associated with the ciphering device and designed for serially transmitted information, and which comprises an input for a sequence of bits to be deciphered, an output for the deciphered bit sequence, and a mixing unit connected between the input and the output, said mixing unit being adapted to receive both the bit sequence to be deciphered and a sequence of code bits for deciphering said bit sequence, and, by a mixing operation, to generate the deciphered bit sequence, and a code unit adapted to generate code bits and comprising a shift register into which bits from the ciphered bit sequence are shifted, and a memory containing code bits and addressed with bits from the shift register.
The use of computers, and especially the transmission of information between computers, has given rise to serious security problems. It is in fact relatively easy to tap data transmission, implying that sensitive information may come into the wrong hands. To obviate this risk, the information transmitted is often ciphered.
Data communication normally takes place in binary form and in most of the ciphering systems hitherto known, ciphering takes place on the bit level in that the sequence of 1's and 0's making up the message is mixed in a ciphering device with a sequence of code bits. When deciphering the message, the ciphered bit sequence is mixed with the same code bit sequence, whereby the message is received in clear.
In hitherto known ciphering devices, the generation of code bits however takes a long time, causing delays in the transmission of information. This means that it is necessary either to decrease the rate at which the transmitter transmits the information or to provide buffers in the ciphering unit. In the latter case, measures must be taken to ensure that information is not lost when the receiving unit emits a signal indicating that it is no longer ready to receive information. Another difficulty resides in synchronizing the generation of code bits. In some devices (see e.g. GB 1,388,035), the information transmission is interrupted at regular intervals for checking whether the code bits in the ciphering and the deciphering device are synchronized. A third problem arises when the ciphering and the deciphering device should be linked to each other after an interruption of the data transmission. Such linking should preferably be effected rapidly and easily without any loss of information and without transmission of information that may give an indication of how the code bits are generated.
The above-mentioned problems entail that known ciphering devices become very expensive since a large number of sophisticated circuits are required for solving the synchronization and link-up problems. Further, the known devices cannot be used in systems with severe demands on a high transmission rate.
For parallel transmission, the above-mentioned synchronization and link-up problems have however been solved by means of a ciphering device shown in U.S. patent specification 4,431,865, which comprises a logic unit in which parallel-transmitted words to be ciphered are mixed with code words to obtain the ciphered words. The code words are generated by supplying the output signal from the logic unit, i.e. the ciphered words, to an addressing circuit comprising a parallel-to-series converter, a shift re
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Cangialosi Salvatore
Datakonsult I Malmo AB
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