CIF converter with reduced multipliers

Facsimile and static presentation processing – Static presentation processing – Attribute control

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358 12, H04N 1120

Patent

active

052725200

ABSTRACT:
A CIF converter has N multipliers (where N is smaller than five) and N integrators connected respectively to the outputs of the N multipliers. Every five horizontal lines of an input NTSC or PAL television signal is stored in memory. On a pixel-by-pixel basis first and second half segments of a luminance component of the stored lines and I and Q chrominance components of the stored lines are transferred from corresponding pixel positions of the memory to the N multipliers at a speed higher than the speed at which the input signal is stored into the memory, and weighted by tap weight coefficients having unique values corresponding respectively to the five horizontal lines. The weighted five-line pixel data of each of the video signal components are then summed by each integrator and stored back into the memory and sequentially read therefrom at a speed equal to the writing speed.

REFERENCES:
patent: 4587556 (1986-05-01), Collins
Signal Processing of HDTV, II; Proceedings of the Third International Workshop of HDTV, Turin, Ital, Aug. 30-Sep. 1, 1989, (1990 Ed.), pp. 587-594, A Flexible Architecture for a HDTV Codec Based on DCT, Mario Barbero et al.
IEEE International Solid State Circuits Conference, No. 31, Feb. 17, 1988, New York, pp. 156-157, 344; A 20-ns CMOS Micro-DSP Core for Video-Signal Processing, Baji et al.
IEEE Journal on Selected Areas in Communication, vol. 6, No. 3, Apr. 1988, New York, pp. 513-519, A Single-Board Video Signal Processor Module Employing Newly Developed LSI Devices, Harasaki et al.
IEEE Global Telecommunications Conference & Exhibition, "Communications for the Information Age", Hollywood, Fla., Motion Video Coding in CCITT SG XV--The Codec Picture Format, Nicol et al., Nov. 28-Dec. 1, 1988.

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