Chunky binary multiplier and method of operation

Details Chunky binary multiplier and method of operation Chunky binary multiplier and method of operation

1993-06-28

1994-07-05

Malzahn, David H.

Boots, shoes, and leggings

364757, G06F 750, G06F 752

Patent

active

053273680

ABSTRACT:
A fast binary reduction tree of the type used in high speed digital computer multiplication circuits is disclosed having chunky adders formed by sub-dividing carry propagate adders into chunks of equal bit length such that chunk addition can be initiated in parallel. In the tree, chunky adders with the same chunk size and offset can be cascaded by connecting the carry-outs of one adder to the carry-ins of another, while carry-outs from adders having different offsets can be interleaved to form new partial product terms for input to the next adder level. The chunky adder tree reduces the number of levels without significantly increasing the computation time at each level, thereby increasing the overall computational speed of the circuit.

REFERENCES:
patent: 3947671 (1976-03-01), Geng et al.
patent: 4228520 (1980-10-01), Letteney et al.
patent: 4901270 (1990-02-01), Galbi et al.
patent: 4914617 (1990-04-01), Putrino et al.
Weinberger, "A 32-Bit Adder Using Partitioned Memory Arrays as Universal Logic Elements" IBM Tech. Disclosure Bulletin vol. 14 No. 1 Jun. 1971 p. 205-207.

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