Chopping and oversampling ADC having reduced low frequency...

Details Chopping and oversampling ADC having reduced low frequency... Chopping and oversampling ADC having reduced low frequency...

2008-04-22

2008-04-22

Mai, Lam T. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

07362255

ABSTRACT:
An integrated circuit includes an analog-to-digital (ADC) portion and a processor portion. The processor portion generates high frequency noise. The ADC portion includes chopper switches, an ADC, a first low-pass filter (LPF), an inverter, and a second LPF. An analog sensor signal is chopped by the chopper switches at a chopping frequency below the processor noise frequency. The ADC performs conversions a rate higher than the chopper frequency such that multiple first conversions are performed when the chopper switches are in a first configuration and multiple second conversions are performed when the chopper switches are in a second configuration. The first LPF attenuates the high frequency noise, converts the first conversions into first information, and converts the second conversions into second information. The inverter inverts the second information. The second LPF attenuates transposed 1/F noise and converts the first information and the inverted second information into ADC output values.

REFERENCES:
patent: 5148167 (1992-09-01), Ribner
patent: 5459432 (1995-10-01), White et al.
patent: 6411242 (2002-06-01), Oprescu et al.
patent: 6639532 (2003-10-01), Liu et al.
Y. -H. Chang et al., “Chopper-Stabilized Sigma-Delta Modulator”, Proc. ISCAS, vol. 2, pp. 1286-1289 (May 1993).
K. Ishida et al., “Chopper-Stabilized High-Pass Sigma Delta Modulator Utilizing A Resonator Structure”, IEEE Transactions On Circuits And Systems-II: Analog And Digital Signal Processing, vol. 50, No. 9, pp. 627-631 (Sep. 2003).

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