Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-06-29
2001-08-07
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S063000
Reexamination Certificate
active
06271691
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-185113, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a voltage comparison circuit formed into a semiconductor integrated circuit, and in particular, to a chopper type voltage comparison circuit using CMOS clocked inverter circuits to amplify a difference between an input voltage and a reference voltage, the circuit being used, for example, in a sequential-comparison analog digital converting circuit (an AD converter).
A CMOS type sequential-comparison AD converter comprises a plurality of chopper type voltage comparison circuits connected together to amplify a difference between a conversion voltage input (an input signal voltage) and a local analog voltage (a reference voltage). An output voltage from the plurality of connected chopper type voltage comparison circuits is input to a code generating logic circuit to generate a digital code, which is then input to a local AD converting circuit to generate a local analog voltage.
FIG. 5
shows an example of a conventional chopper type voltage comparison circuit used in a sequential-comparison AD converter.
In
FIG. 5
, analog switches SW
1
and SW
2
select a conversion voltage input (a signal input voltage Vin) and a local analog voltage (a reference voltage for comparison Vref) in a switching fashion. The analog switch SW
1
is controlled by complementary clock signals (F
1
, /F
1
). The analog switch SW
2
is controlled by complementary clock signals (F
2
, /F
2
).
In the AD converter in
FIG. 5
, for example, three chopper type voltage comparison circuits are connected together. Each of the chopper type voltage comparison circuits comprises a capacitor having the input voltage or the reference voltage supplied to one end thereof depending on whether a voltage input operation (a sample period) or a voltage comparison operation (a comparison period) is to be performed, and an amplifying circuit having a CMOS inverter circuit for voltage amplification connected to the other end of the capacitor and an analog switch for bias initialization connected between an input node and an output node of the inverter circuit. Correspondingly to the first, second, and third comparison circuit, the capacitors are denoted by C
1
to C
3
, the CMOS inverter circuits are denoted by INV
1
to INV
3
, the analog switches are denoted by SW
3
to SW
5
, and the amplifying circuits are denoted by AMP
1
to AMP
3
. The first comparison circuit comprises the capacitor C
1
, and the amplifying circuit AMP
1
having the CMOS inverter circuit INV
1
and an analog switch SW
3
. The second comparison circuit comprises the capacitor C
2
, and the amplifying circuit AMP
2
having the CMOS inverter circuit INV
2
and an analog switch SW
4
. The third comparison circuit comprises the capacitor C
3
, and the amplifying circuit AMP
3
having the CMOS inverter circuit INV
3
and an analog switch SW
5
.
The analog switches SW
3
to SW
5
are each controlled by a clock signal F
3
and an inverted clock signal /F
3
obtained by the inverter circuit INV
4
by inverting the clock signal F
3
. In addition, NMOS transistors NT
1
to NT
3
are each connected between a ground node and an input node of a corresponding one of the inverter circuits INV
1
to INV
3
, with an enable control signal En
1
commonly applied to the gates of the NMOS transistors NT
1
to NT
3
in a predetermined timing. Thus, the NMOS transistors NT
1
to NT
3
are switched on in the predetermined timing to set the input node of each inverter circuit INV
1
to INV
3
to a ground potential.
The three connected chopper type voltage comparison circuits have two inverter circuits INV
5
, INV
6
connected on their output side.
Next, the operation of the chopper type voltage comparison circuit of an AD converter shown in
FIG. 5
will be described.
First, during a sample period, the analog switch SW
2
is controlled to be non-conductive, while the analog switches SW
1
, SW
3
, SW
4
, and SW
5
are controlled to be conductive. Thus, input and output signals of the inverter circuits INV
1
, INV
2
, and INV
3
are set to be short-circuited, and the input and output nodes of each of the inverter circuits INV
1
, INV
2
, and INV
3
are set to have the same voltage. That is, bias voltages at the input and output nodes of each inverter circuit INV
1
, INV
2
, and INV
3
are initialized. In the meantime, the input voltage Vin=Va is charged to the capacitor C
1
through the analog switch SW
1
.
At this time, a potential Vb at the input node of the inverter circuit INV
1
and a potential Vc at the output node thereof are each biased to a circuit threshold (substantially half a power supply voltage VDD) of the inverter INV
1
, and a charge corresponding to Vin-Vb is stored in the capacitor C
1
. Likewise, a charge is stored in the capacitors C
2
and C
3
.
Next, during a comparison period, the analog switches SW
1
, SW
3
, SW
4
, and SW
5
are controlled to be non-conductive, while the analog switch SW
2
is controlled to be conductive. Thus, the reference Vref is applied to the capacitor C
1
through the analog switch SW
2
, and the potential Vb at the input node of the inverter INV
1
changes depending on the difference between the input voltage Vin and the reference voltage Vref, with this change amplified by the three inverter circuits INV
1
to INV
3
. An output voltage from the final stage inverter circuit INV
3
is input further through the two inverter circuits INV
5
, INV
6
to a code generating logic circuit (not shown), which then determines which of the input voltage Vin and reference voltage Vref is higher to generate a digital code depending on a result of the determination.
The above described operations during the sample period and during the comparison period are sequentially performed until the individual bits of the digital code have been determined ranging from a most significant bit (MSB) to a least significant bit (LSB).
It is assumed that in response to a request for a low voltage operation of the AD converter, the power supply voltage VDD is lowered, with the threshold voltage of each transistor retaining at the same value as in the prior art.
In this case, when the power supply voltage VDD is reduced down to a value (for example, 1.8V ) equal to or lower than the sum of the absolute value |Vtp| (for example, 0.9V ) of the threshold voltage of a PMOS transistor of each inverter circuit INV
1
to INV
3
and a threshold voltage Vtn (for example, 0.9V ) of the NMOS transistor, a voltage between a gate and a source of each of the MOS transistors becomes extremely low to disable normal operations of the inverter circuits INV
1
, INV
2
, and INV
3
. Additionally, in this case, when an “H” level and “L” level of a control signal for the analog switches SW
3
, SW
4
, and SW
5
is 1.8V and 0V, respectively, a voltage between a gate and a source of each of the MOS transistors of each analog switch SW
3
, SW
4
, and SW
5
becomes extremely low to disable normal operations of the analog switches SW
3
, SW
4
, and SW
5
.
Accordingly, the potentials at the input and output nodes of each inverter circuit INV
1
, INV
2
, and INV
3
cannot be biased to the corresponding circuit thresholds. Thus, to enable the AD converter to operate at a low power supply voltage, the threshold voltage of each transistor must be reduced.
When the threshold voltage of each transistor is reduced, a leakage current from the transistors constituting the analog switches SW
3
, SW
4
, and SW
5
and the inverter circuits INV
1
, INV
2
, and INV
3
increases in the non-conductive state. A leakage current flowing through the output node and input node of each inverter circuit INV
1
, INV
2
, INV
3
hinders the original potential Vb of the input node from being maintained.
If such a phenomenon occurs during the voltage comparison operation, the voltage compariso
Inoue Eisuke
Maruyama Kimio
Toyoda Kenji
Kabushiki Kaisha Toshiba
Nguyen Hiep
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Wells Kenneth B.
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