Chopper type comparator

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307355, 307362, 307443, H03K 19003, H03K 524, H03K 1716

Patent

active

050417444

ABSTRACT:
The present invention provides a logic circuit comprising a first power terminal, a second power terminal set at a higher potential than the first power terminal, a first FET of a first conductivity having a current path coupled to the first power terminal, a second FET of a second conductivity having a current path coupled to the second power terminal, and an input terminal commonly coupled to gate terminals of the first and second FETs, the first FET and the second FET having a relationship expressed approximately by the following equation: ##EQU1## where R.sub.S is a resistance of a resistor element parasitically produced between the first power terminal and the current path of the first FET. R.sub.D is a resistance of a resistor element parasitically produced between the second power terminal and the current path of the second FET, W.sub.N is a channel width of the first FET, W.sub.P is a channel width of the second FET, L.sub.N is a channel length of the first FET, L.sub.P is a channel length of the second FET, .mu..sub.N is a first carrier mobililty of the first FET, and .mu..sub.P is a second carrier mobility of the second FET.

REFERENCES:
patent: 4760287 (1988-07-01), Goto et al.
patent: 4845383 (1989-07-01), Iida
Kuboki et al., "Analysis and Evaluation of CMOS Chopper Type Comparator," The Transactions of the Institute of Electronics and Communication Engineers of Japan, vol. J67-C, No. 5, pp. 443-450, May 1984.

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