Chopper stabilized analog multiplier

Telecommunications – Receiver or analog modulated signal frequency converter – Noise or interference elimination

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C455S314000, C455S323000

Reexamination Certificate

active

10932469

ABSTRACT:
A method and circuit to eliminate an offset noise, which may be produced at or near DC (zero Hertz) in an analog, linear multiplier, is described. An input signal is chopped (converted to another frequency) by a first chopper, shifting a frequency of the input signal such that the multiplier output signal is shifted away from DC. An output signal of the multiplier is subsequently chopped again by a second chopper employing the same chopping frequency as the first chopper. This converts a frequency of the output signal to a desired frequency at or near DC. The double chopping also shifts the offset noise produced by the multiplier to a frequency, that is higher than the frequency of the output signal. The offset noise can then be removed by a low-pass filter leaving the output signal without the offset noise.

REFERENCES:
patent: 5486788 (1996-01-01), Schlager et al.
patent: 5489868 (1996-02-01), Gilbert
patent: 6204719 (2001-03-01), Gilbert
patent: 6380801 (2002-04-01), McCartney
patent: 6445726 (2002-09-01), Gharpurey
patent: 6639460 (2003-10-01), Botker
patent: 6674322 (2004-01-01), Motz
patent: 6707336 (2004-03-01), Reber
Abidi, Asad A.. 2004. “RF CMOS Comes of Age.”IEEE Journal of Solid-State Circuits39:4 (Apr.) 549-561.
Bakker, Anton et al. 2000. “A CMOS Nested Chopper Instrumentation Amplifier with 100nV Offset.”IEEE International Solid-State Circuits Conference(Feb.) 156-157, 452.
Bult, Klaas and Hans Wallinga. 1987. “A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation.”IEEE Journal of Solid-State Circuits22:3, (Jun.) 357-365.
Enz, Christian C. and Gabor C. Temes. 1996. “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization.” Proceedings of the IEEE 84:11 (Nov.) 1584-1614.
Gilbert, Barrie. 1968. “A New Wide-Band Amplifier Technique.”IEEE Journal of Solid-State Circuits3:4 (Dec.) 353-365.
Gilbert, Barrie. 1968. “A Precise Four-Quadrant Multiplier with Subnanosecond Response.”IEEE Journal of Solid-State Circuits3:4 (Dec.) 365-373.
Kimura, Katsuji. 1994. “A Bipolar Four-Quadrant Analog Quarter-Square Multiplier Consisting of Unbalanced Emitter-coupled Pairs and Expansions of its Input Ranges.”IEEE Journal of Solid-State Circuits29:1 (Jan.) 46-55.
Kimura, Katsuji. 1996. “Some Circuit Design Techniques for Low-Voltage Analog Functional Elements Using Squaring Circuits.”IEEE Transactions on Circuits and SystemsI 43:7 (Jul.) 559-576.
Soo, David C. and Robert G. Meyer. 1982. “A Four-Quadrant NMOS Analog Multiplier.”IEEE Journal of Solid-State Circuits17:6 (Dec.) 1174-1178.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Chopper stabilized analog multiplier does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chopper stabilized analog multiplier, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chopper stabilized analog multiplier will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3774638

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.