Electric power conversion systems – Current conversion – Using semiconductor-type converter
Reexamination Certificate
2000-10-11
2001-10-16
Wong, Peter S. (Department: 2838)
Electric power conversion systems
Current conversion
Using semiconductor-type converter
C363S017000, C363S132000
Reexamination Certificate
active
06304474
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chopper circuit, a chopper circuit control method, a chopper-type charging circuit, an electronic device, and a timekeeping apparatus.
2. Related Art
A chopper-type charging circuit is known as a charging circuit for charging a capacitor or a battery, with alternating current electrical power generated by an electrical generator.
FIG. 12
of the appended drawings is a circuit diagram of a chopper-type charging circuit. This chopper-type charging circuit
1
is formed by an oscillator circuit
2
, which outputs a clock signal CL, and comparators COM
1
and COM
2
, which perform a comparison between the voltages at output terminals A and B of an alternating current electrical generator AG and a terminal voltage VDD of a power supply, and an AND circuit
3
, which calculates the logical product of the output signals SP
1
and SP
2
of the comparators COM
1
and COM
2
and the clock signal CL.
The chopper-type charging circuit also has a large-capacitance capacitor
4
for storing a charging current, and P-channel FETs P
1
and P
2
, which are on/off controlled by the output signals SP
1
and SP
2
of the comparators COM
1
and COM
2
, and N-channel FETs N
1
and N
2
, which are on/off controlled by an output signal SN of the AND circuit
3
.
In this configuration, diodes D
1
, D
2
, D
3
, and D
4
are parasitic diodes of the P-channel FETs P
1
and P
2
and the N-channel FETs N
1
and N
2
, respectively.
The operation of the chopper-type charging circuit is described below, with reference made to the timing diagram shown in FIG.
13
.
In
FIG. 13
, the assumption is that until a time ta, the voltages at the output terminals A and B is no greater than the terminal voltage VDD, the comparator COM
1
and COM
2
output signals SP
1
and SP
2
being held at a high level, and the P-channel FETs P
1
and P
2
being in the off state.
At the time ta, when the clock signal CL changes to the high level, the output signal SN of the AND circuit
3
changes to the high level, so that the N-channel FETs N
1
and N
2
change to the on state, a closed loop being formed by the alternating current generator AG and the N-channel FETs N
1
and N
2
.
In the above case, the alternating current generator AG generates an electromotive force and, for example, when the output terminal A reaches a positive potential with respect to the output terminal B, as shown by the symbol &agr; in
FIG. 12
, a current i1 flows through a path from the alternating current generator AG, to the N-channel PET N
1
, and then to the N-channel FET N
2
.
At the time tb, when the clock signal CL falls to the low level, the output signal SN of the AND circuit
3
changes to the low level, so that the N-channel FETs N
1
and N
2
are placed in the off state, thereby cutting off the above-noted current path.
In the above case, because of the current that flows during the time when the clock signal CL is at the high level (hereinafter referred to as the shorted period), the energy is stored in the inductance of the generator coil of the alternating current generator AG, this energy causing a rise in the voltage at the output terminal A.
Next, at the time tc, when the voltage on the terminal A rises to above the terminal voltage VDD of the large-capacitance capacitor
4
, the output signal SP
1
of the comparator COM
1
changes to the low level, so that the P-channel FET P
1
switches to the on state.
As a result, as shown by the symbol &bgr; in
FIG. 12
, a current i2 flows through a current path from the diode D
4
of the N-channel FET N
2
, to the alternating current generator AG, to the P-channel FET P
1
, and then to the large-capacitance capacitor
4
. Thus, the charging of the large-capacitance capacitor
4
begins.
As the charging continues, energy stored in the inductance of the generator coil is gradually released, so that the charging current i2 gradually decreases. When the voltage on the output terminal A falls below the terminal voltage VDD of the large-capacitance capacitor
4
, the output signal SP
1
of the comparator COM
1
changes to the high level, so that the P-channel FET P
1
switches to the off state, thereby cutting off the above-noted charging current path.
That is, until the voltage at the output terminal A falls below the terminal voltage VDD of the large-capacitance capacitor
4
, the AND circuit
3
holds the N-channel FETs N
1
and N
2
in the off state, so that charging is continued. Additionally, when the amount of electricity generated by the alternating current generator AG is large and the amount of energy stored in the inductance of the generator coil is large, charging continues even after switching to the shorted period, thereby making the charging time long, so that it commensurately eats away the shorted period.
In the case in which the electromotive force of the alternating current generator AG is generated and the output terminal B reaches a potential that is positive potential with respect to the output terminal A, the direction of the current i1 flowing during the above-noted shorted period reverses, so that the voltage on the output terminal B rises. As a result, the charging current i2 flows through the path from the diode D
3
of the N-channel FET N
1
, and the alternating current generator AG, and the P-channel FET P
2
, and then the large-capacitance capacitor
4
, resulting in the charging of the large-capacitance capacitor
4
.
Thus, in a chopper-type charging circuit of the past, by repeatedly performing shorting and voltage rise of the circuit in accordance with the clock signal, the electromotive force of an alternating current generator, which has a small, non-uniform amount of generated electricity, is converted to a chopper voltage that charges a large-capacitance capacitor. In the case in which there is a large amount of energy stored in the inductance of the generator coil of the chopper-type charging circuit
1
, or in which the input energy is large, the shorted period of the chopper is disabled, so that priority is given to charging by non-chopped operation. By performing charging by switching between chopper and non-chopped operation, it is possible to efficiently charge the large-capacitance capacitor.
In a chopper-type charging circuit using a unidirectional unit having a configuration in the voltage across the terminals of this type of field-effect transistor is comparator using a comparator, one method of that can be envisioned of improving the charging efficiency by reducing charging path loss is that of making the conduction resistance (on-state resistance) between the source and drain of the field-effect transistor as small a value as possible.
However, if this conduction resistance is made small, the source-drain voltage of the field-effect transistor is becomes small. Therefore, the potential at the collector input terminal falls below a threshold value, and the field-effect transistor goes into the off state, after which the difference in potential between the two input terminals of the comparator rises because of the forward voltage drop of the diode, resulting in the field-effect transistor immediately going into the on state, with this operation being repeated. In the case of such low-current conduction, a phenomenon known as chattering occurs, in which the field-effect transistor repeated alternates between the on and off states.
That is, at the time td in the timing diagram of
FIG. 13
, when the voltage on the output terminal A falls below the terminal voltage VDD of the large-capacitance capacitor
4
, the output signal SP
1
of the comparator COM
1
changes to the high level, and the P-channel FET P
1
goes into the off state. However, because the charging current i2 flowing in the P-channel FET P
1
immediately before the switching of the output signal SP
1
of the comparator COM
1
to the high level (the region of time td) is small, the voltage drop due to the on resistance oft eh P-channel FET P
1
is small. For this reason, when the signal SP
1
changes to the
Seiko Epson Corporation
Vu Bao Q.
Watson Mark P.
Wong Peter S.
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