Chipset synchronization arrangement

Details Chipset synchronization arrangement Chipset synchronization arrangement

1983-08-01

1985-04-30

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307601, 307603, 307605, 307608, H03K 5135, H03K 514, H03K 512, H03K 386

Patent

active

045146470

ABSTRACT:
Each chip of a microprocessor chipset is synchronized by an associated controller which adjusts a control signal for controlling the delay of a variable delay circuit during each operating cycle. The controller tailors the control signal for each chip by an op-amp which compares the output of an internal clock in each chip with a reference system clock.

REFERENCES:
patent: 3440452 (1969-04-01), Boehm
patent: 3725793 (1973-04-01), Phillips
patent: 3755748 (1973-08-01), Carlow et al.
patent: 3778784 (1973-12-01), Karp et al.
patent: 3986046 (1976-10-01), Wunner
patent: 4021784 (1977-05-01), Kimlinger
patent: 4122361 (1978-10-01), Clemen et al.
patent: 4379974 (1983-04-01), Plachno

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