Chiprate correction in digital transceivers

Telecommunications – Transmitter and receiver at same station – With frequency stabilization

Reexamination Certificate

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C455S076000, C455S173100, C455S255000, C455S256000, C455S257000, C455S258000, C455S259000, C260S001000, C260S001000, C375S343000, C375S344000, C375S375000, C375S376000, C370S505000, C370S506000, C370S507000, C370S508000

Reexamination Certificate

active

07133647

ABSTRACT:
A transceiver for a code division multiple access communication system comprises a receiver to receive coded information signals and a transmitter to transmit coded information signals. A local oscillator provides a time and frequency reference for the receiver and the transmitter. A timing controller provides timing signals for the receiver and the transmitter. A signal processor decodes received signals to determine a common error associated with the timing controller. A timing correction circuit smoothly adjusts the timing of the coded information signals transmitted by the transmitter responsive to the timing error to reduce the timing error over a desired time interval.

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