Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
1998-04-02
2002-04-02
Williams, Alexander O. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S700000, C257S723000, C257S738000, C257S737000, C257S778000, C257S686000, C257S685000, C361S769000, C361S767000, C361S790000, C361S735000, C361S729000, C324S755090, C324S765010
Reexamination Certificate
active
06365975
ABSTRACT:
BACKGROUND OF THE INVENTION
Semiconductor chips commonly incorporate myriad electronic elements such as transistors, capacitors, resistors and the like, together with more complex electronic elements such as logic gates, amplifiers, comparators, and many other passive and active electrical components. These elements typically are provided in one or more layers extending parallel to the front and back surfaces of the chip. The various electronic elements of the chip typically are interconnected with one another by metallic traces extending within the chip in the horizontal or “X” and “Y” directions and metallic vias extending in the vertical or “Z” direction. Typically, the traces and vias are formed of conductive material deposited during fabrication of the chip as, for example, aluminum or polysilicon. The traces and vias used to interconnect the electronic elements of the chip with one another complicate design and fabrication of the chip.
Moreover, the traces which are fabricated during manufacture of the chip do not always provide optimum electrical characteristics. For example, the traces typically are formed from aluminum, which has a relatively high resistivity. Although processes for fabricating traces in a chip from low-resistivity metals such as copper are known, these processes impose special requirements in chip fabrication. Further, even if a low-resistivity metal is employed, the size and hence the cross-sectional area of traces which can be accommodated within a chip are subject to severe limitations. Traces extending within a chip often follow indirect routes because other elements of the chip lie in a direct route between the electronic elements connected by the trace.
Additionally, chips must be connected to external circuit elements. In the conventional approach to chip packaging, each chip is incorporated in a separate package bearing leads or other external connecting elements. Contacts on the surface of the chip are connected to these external connecting elements. The external connecting elements on the package are connected to a conventional circuit board or other circuit-bearing substrate. Alternatively, several chips may be mounted in a single package, commonly referred to as a “multichip module.” These chips may be connected to one another and to a common set of external connecting elements, so that the entire assembly can be mounted to the substrate as a unit. In yet another alternative, the chip itself is attached directly to the substrate.
As described in Arima et al., U.S. Pat. No. 5,281,151, a package in the form of a rigid ceramic board may be provided with a set of “thin film” circuit layers overlying the ceramic board. The thin film layers include metallic traces on a material such as polyimide which has a relatively low dielectric constant. A chip is mounted to the thin film layers by solder balls in engagement with contacts on the chip. A signal can be routed from point to point within the chip along a signal path through a solder ball at one location on the chip, along a metallic trace of the thin film element and back into the chip through a solder ball at another location on the chip. The thin film layer assertedly provides low resistance and relatively rapid signal transmission between elements of the chip.
As described in commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,455,390, 5,518,964 and the corresponding WO 96/02068 published Jan. 25, 1996, as well as in co-pending, commonly assigned U.S. patent application Ser. No. 08/653,016, filed May 24, 1996, now U.S. Pat. No. 5,688,716; Ser. No. 08/678,808 filed Jul. 12, 1996 as well as Ser. No. 08/532,528 filed Sep. 22, 1995, and the corresponding International Publication No. WO 97/11486 published Mar. 27, 1997, the disclosures of which are all incorporated by reference herein, it is desirable to provide interconnections between the contacts on a chip and external circuitry by providing a further dielectric element, which may be referred to as a “interposer” or “chip carrier” having terminals. Terminals on the dielectric element are connected to the contacts on the chip by flexible leads. The terminals on the dielectric element may be connected to the substrate as, for example, by solder bonding the terminals to contact pads of the substrate. The dielectric element remains movable with respect to the chip so as to compensate for thermal expansion and contraction of the components. That is, various parts of the chip can move with respect to the dielectric element as the chip grows and shrinks during changes in temperature. In a particularly preferred arrangement, a compliant dielectric layer is provided as a separate component so that the compliant layer lies between the chip and the terminals. The compliant layer may be formed from a soft material such as a gel, elastomer, foam or the like. The compliant layer mechanically decouples the dielectric element and terminals from the chip and facilitates movement of the dielectric element relative to the chip. The compliant layer may also permit movement of the terminals in the Z direction, towards the chip, which further facilitates testing and mounting of the assembly.
As disclosed in copending, commonly assigned U.S. patent application Ser. No. 08/641,698, and International Publication No. WO 97/40958 the disclosure of which is also incorporated by reference herein, the electrically conductive parts on the dielectric element may be connected to the chip by masses of a fusible, electrically conductive material which is adapted to melt at temperatures encountered during processing or operation of the assembly. These masses may be constrained by a surrounding compliant dielectric material so that they remain coherent while in a molten state. The molten masses provide another form of deformable conductive element, which allows movement of the flexible dielectric element relative to chip. As further disclosed in commonly assigned patents and patent applications, one or more chips may be mounted to a common dielectric element or interposer, and additional circuit elements also may be connected to such a dielectric element. The dielectric element may incorporate conductive traces which form interconnections between the various chips and electronic components of the assembly.
Designers of multichip modules have provided connections between different chips as transmission lines including plural conductors. As discussed in Multichip Module Technologies and Alternatives-The Basics, Doane and Franzon, eds., Chapter 11, pp. 525-568, Electrical Design of Multichip Modules (1993), a signal line extending between a pair of digital elements on different chips of a module may extend over a reference plane, such as a ground or power plane, so that the signal line, reference plane and intervening dielectric constitute a controlled-impedance transmission line.
Despite all of these efforts in the art, however, there are significant needs for improvements in semiconductor chips and assemblies incorporating the same. In particular, there are needs for improved chip assemblies which can provide rapid and reliable propagation of signals between electrical elements within a single chip.
SUMMARY OF THE INVENTION
The present invention addresses these needs.
A microelectronic assembly in accordance with one aspect of the present invention incorporates a first semiconductor chip including a plurality of electronic elements adapted to receive and send signals. The electronic elements of the chip may include any of the electronic components mentioned above and any other types which may incorporated in a chip. The chip includes a front surface having contacts thereon. At least some of the electronic elements are connected to the contacts. The assembly further includes a dielectric element separate from the chip. The dielectric element has a plurality of conductive interconnect traces on it.
Most preferably, the dielectric element is movable with respect to the chip. In this case, the assembly includes a plurality of deformable conductive elements such as fusible mass
DiStefano Thomas H.
Smith John W.
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
Williams Alexander O.
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