Chip topography for MOS interface circuit

Details Chip topography for MOS interface circuit Chip topography for MOS interface circuit

1974-10-30

1976-07-06

Wise, Edward J.

Communications: electrical

Digital comparator systems

235156, 307213, 307303, G06F 1300, H01L 2500

Patent

active

039684784

ABSTRACT:
The chip architecture of an MOS peripheral interface adaptor chip includes data bus buffers arranged along one edge of the chip, peripheral interface buffers arranged along an opposite edge of the chip and a register section centrally located on the chip. Separate power supply buses are used to supply a ground voltage to the buffer and register sections. Data bus buffers are arranged to allow the pins of the enclosing semiconductor package to correspond to data bus pins of a separate microprocessor chip. Register sections are offset on the surface of the peripheral interface adaptor chip in such a way as to facilitate nesting of the conductors coupled to the buffer circuit section. Identical buffer cells and custom drawn cells are both utilized so as to optimize use of semiconductor chip area.

REFERENCES:
patent: 3462742 (1969-08-01), Miller et al.
patent: 3716843 (1973-02-01), Schmitt et al.
patent: 3740723 (1973-06-01), Beausoleil et al.
patent: 3745532 (1973-07-01), Erwin
patent: 3760367 (1973-09-01), Kortenhaus
patent: 3798606 (1974-03-01), Henle et al.
patent: 3800129 (1974-03-01), Umstattd

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