Chip topography for MOS integrated circuitry microprocessor chip

Details Chip topography for MOS integrated circuitry microprocessor chip Chip topography for MOS integrated circuitry microprocessor chip

1974-10-30

1976-10-19

Shaw, Gareth D.

Communications: electrical

Digital comparator systems

G06F 100

Patent

active

039874184

ABSTRACT:
The chip architecture of an MOS microprocessor chip includes data bus input-output buffer circuitry located along the lower right hand edge of the chip. High order address buffer output circuitry is located along the bottom of the chip. Directly to the left of the data bus input-output buffer circuitry is the arithmetic logic unit circuitry, and to the right of this and adjacent to the high order address bit buffer circuitry is located a register section including first accumulator register, a second accumulator register, high and low order index registers, a high order incrementer and an associated program counter, a low order incrementer and associated program counter, a high order stack pointer register and a low order stack pointer register, and a temporary register arranged on the surface of the microprocessor chip in a particular sequence. To the left of the register section and along the lower left hand edge of the chip is located a plurality of low order address bit buffer circuits. Above and coupled to the register section and to the arithmetic logic unit is located a plurality of bootstrap driver circuits for driving signals which enable programmed data transfers between the various registers, the arithmetic logic unit and a plurality of internal data bus and address bus conductors coupled to the data bus input-output buffer circuitry and the high order and the low order address bit buffer circuits, respectively. Read/write circuitry, a condition code register, decision logic circuitry, and an instruction register are located in sequence along the upper righthand edge of the chip. To the left of the decision logic circuitry and the condition code register and above the bootstrap driver circuitry and coupled thereto is a logic control circuitry section. Above the logic control circuitry and along the upper edge of the chip to the left of the instruction register is located an instruction decoder circuitry section. Along the upper lefthand edge of the chip is located input-output control circuitry and look-ahead circuitry for the instruction decoder. Between the lefthand portion of the logic control circuitry and the right hand portion of the I/O control circuitry is located timing generator circuitry coupled to the logic control circuitry for enabling the selected logic gates therein, which are selected and driven by the instruction decoder.

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