Chip topography for MOS Data Encryption Standard circuit

Details Chip topography for MOS Data Encryption Standard circuit Chip topography for MOS Data Encryption Standard circuit

1980-06-05

1985-09-24

Heckler, Thomas M.

Boots, shoes, and leggings

178 2209, G06F 100

Patent

active

045436460

ABSTRACT:
An optimum chip topography for a MOS LSI Data Encryption Standard (DES) circuit, including interface and input/output circuitry disposed around the periphery of the chip, control circuitry disposed in a substantially rectangular area across the upper one-third of the surface of the chip, and, disposed on approximately the lower two-thirds of the surface of the chip and perpendicular to the control circuitry area, and arranged from one side of the chip to the other side of the chip, a key register, permuted choice circuitry, a first combinatorial circuit, a right data register, a second combinatorial circuit, a left data register, a P-combinatorial circuit, a first programmable logic arry group, and a second programmable logic array group. The bonding pad sequence for the MOS DES circuit chip is selected to allow the chip to be placed in either a 40-pin dual-in-line package or a 28-pin dual-in-line package. The bonding pad sequence for the MOS DES circuit chip is also selected to allow optimum arrangement of packages containing the DES circuit chips on a printed circuit board. Repetitive circuit cells and custom drawn circuit cells are both utilized so as to optimize use of semiconductor chip area.

REFERENCES:
patent: 3958081 (1976-05-01), Ehrsam
patent: 3968478 (1976-07-01), Mensch
patent: 3987418 (1976-10-01), Buchanan
patent: 4144561 (1979-03-01), Tu
patent: 4393464 (1983-07-01), Knapp et al.
patent: 4433378 (1984-02-01), Leger
"Data Security Chip", Finger et al., IBM Technical Disclosure Bulletin, vol. 20, No. 9 (Feb. 1978), pp. 3543-3544.

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