Chip topography for integrated circuit communication controller

Details Chip topography for integrated circuit communication controller Chip topography for integrated circuit communication controller

1980-12-12

1983-07-12

Springborn, Harvey E.

Boots, shoes, and leggings

364200, 357 45, G06F 1300, H01L 2500

Patent

active

043934641

ABSTRACT:
An integrated circuit for operatively connecting a plurality of peripheral devices to a processor includes first, second, third and fourth sequentially located edges forming a rectangle. The integrated circuit includes two independent full duplex, master peripheral ports in which each port provides two character buffering on both input and output channels. Data may be transmitted using two message formats at two different clock frequencies with each channel having simultaneous sending and receiving capabilities. Data processing circuits are located adjacent the first edge which connects to the processor while the port control circuitry is located adjacent the third edge of the chip which connects to the peripheral devices.

REFERENCES:
patent: 3968478 (1976-07-01), Mensch, Jr.
patent: 4021781 (1977-05-01), Caudel
patent: 4125854 (1978-11-01), McKenny
patent: 4144561 (1979-03-01), Tu et al.
patent: 4278897 (1981-07-01), Ohno et al.

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