Chip topography for a MOS disk memory controller circuit

Details Chip topography for a MOS disk memory controller circuit Chip topography for a MOS disk memory controller circuit

1983-09-23

1987-03-10

Thomas, James D.

Boots, shoes, and leggings

G06Z 100, G06Z 1300

Patent

active

046494740

ABSTRACT:
An improved chip topography for a disk memory controller circuit is provided which includes chip buffer circuitry disposed around the periphery of the chip wherein the chip buffer circuitry forms a quadrilateral outer framework on the chip and data I/O buffer circuitry forms a first side of the quadrilateral outer framework; data I/O buffer control circuitry disposed between first and second corners of the chip buffer circuitry and adjacent to the data I/O buffer circuitry; a microcontroller for regulating the functions of the disk memory controller chip wherein a first portion of the microcontroller is disposed adjacent to the data I/O buffer control circuitry and along a part of a second side of the chip buffer circuitry; drive control and unit select registers coupled to the microcontroller and the chip buffer circuitry, and disposed adjacent to the first portion of the microcontroller and along part of a third side and within a third corner of the chip buffer circuitry, said microcontroller further comprising a second portion disposed adjacent to the first portion of the microcontroller and within a third corner and along a part of the third side of the chip buffer circuitry; a read-only-memory (ROM) disposed adjacent to the second portion of the microcontroller along a part of a fourth side of the chip buffer circuitry, said microcontroller further comprising a third portion which is disposed adjacent to the ROM and along a part of the fourth side of the chip buffer circuitry; disk synchronization circuitry disposed adjacent to the third portion of the microcontroller and along a part of the fourth side of the chip buffer circuitry; shift registers disposed adjacent to the disk synchonization circuitry and the third portion of the microcontroller; error checking circuitry disposed adjacent to and between the first and third portions of the microcontroller and also disposed adjacent to the data I/O buffer control circuitry; and a register file disposed adjacent to and between the first and third portions of the microcontroller and also disposed adjacent to the error checking circuitry.

REFERENCES:
patent: 4393464 (1983-07-01), Knapp et al.
patent: 4525801 (1985-06-01), Kuwabara
patent: 4527233 (1985-07-01), Ambrosius et al.
patent: 4549262 (1985-10-01), Chung et al.

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