Chip topography for a MOS disk memory controller circuit

Details Chip topography for a MOS disk memory controller circuit Chip topography for a MOS disk memory controller circuit

1983-06-20

1985-10-22

Thomas, James D.

Boots, shoes, and leggings

357 45, G06F 300, G06F 1300, H01L 2706

Patent

active

045492620

ABSTRACT:
An improved chip topography for a disk memory controller circuit is provided which includes electrical interface circuitry disposed around the periphery of the chip and forming an approximately quadrilateral framework surrounding the remainder of the circuitry, a read-only-memory (ROM) disposed in one corner of the interface framework; a microcontroller disposed adjacent to the ROM and along part of a first side of the interface framework; read data processing circuitry disposed adjacent to the microcontroller and within a second corner of the interface framework and along part of a second side thereof; error checking circuitry disposed adjacent to the read data processing circuitry and along part of the second side of the interface framework; the microcontroller also being disposed adjacent to the error checking circuitry and along part of the second side of the interface framework; write data processing circuitry disposed adjacent to the microcontroller along the second side of the interface boundary, within a third corner of the interface framework and along a part of a third side of the interface boundary; the microcontroller also being disposed adjacent to the write data processing circuitry and along the third side of the interface framework; input/output (I/O) buffer/latch circuitry disposed adjacent to the micro controller along the third side of the interface framework, which is also disposed within the fourth corner and along a part of a fourth side of the interface framework, the microcontroller also being disposed adjacent to and between the I/O buffer/latch circuitry and the ROM along the fourth side of the interface framework; and task registers disposed between the microcontroller and the I/O buffer/latch circuitry.

REFERENCES:
patent: 3808475 (1974-04-01), Buelow et al.
patent: 4144561 (1979-03-01), Tu et al.
patent: 4204250 (1980-05-01), Getson et al.
patent: 4393464 (1983-07-01), Knapp et al.
patent: 4433378 (1984-02-01), Leger
patent: 4449202 (1984-05-01), Knapp et al.

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