Chip structure with bumps and testing pads

Details Chip structure with bumps and testing pads Chip structure with bumps and testing pads

2011-07-12

2011-07-12

Andújar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S784000, C257S786000, C257SE23003

Reexamination Certificate

active

07977803

ABSTRACT:
A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization structure comprises a first circuit layer and a second circuit layer over the first circuit layer, and comprises a damascene electroplated copper. The passivation layer is over the metallization structure and dielectric layers, the passivation layer including a first opening exposing a contact point of the metallization structure. The polymer layer is disposed over the passivation layer and the first metal layer, a second opening in the polymer layer being over a second contact point of the first metal layer, the polymer layer covering a top surface and sidewall of the first metal layer. The second contact point is connected to the first contact point through the first opening, the second opening not being vertically over the first opening.

REFERENCES:
patent: 4051508 (1977-09-01), Sato et al.
patent: 6511901 (2003-01-01), Lam et al.
patent: 6590295 (2003-07-01), Liao et al.
patent: 6762117 (2004-07-01), Lam et al.
patent: 6844631 (2005-01-01), Yong et al.
patent: 2003/0197289 (2003-10-01), Lin

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