Chip structure and stacked chip package as well as method...

Details Chip structure and stacked chip package as well as method... Chip structure and stacked chip package as well as method...

2011-06-07

2011-06-07

Huynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S458000, C438S462000, C257S620000, C257SE21237, C257SE21238, C257SE21559

Reexamination Certificate

active

07955897

ABSTRACT:
A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals.

REFERENCES:
patent: 5989982 (1999-11-01), Yoshikazu
patent: 6174751 (2001-01-01), Oka
patent: 7242101 (2007-07-01), Ararao et al.
patent: 2006/0267609 (2006-11-01), Lee et al.

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