Chip structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S738000, C257S780000, C257S781000, C257SE21476, C438S629000

Reexamination Certificate

active

07964973

ABSTRACT:
A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.

REFERENCES:
patent: 3668484 (1972-06-01), Greig et al.
patent: 4051508 (1977-09-01), Sato et al.
patent: 4685998 (1987-08-01), Quinn et al.
patent: 4825276 (1989-04-01), Kobayashi
patent: 5083187 (1992-01-01), Lamson et al.
patent: 5226232 (1993-07-01), Boyd
patent: 5310699 (1994-05-01), Chikawa et al.
patent: 5468984 (1995-11-01), Efland et al.
patent: 5508561 (1996-04-01), Tago et al.
patent: 5532512 (1996-07-01), Fillion et al.
patent: 5534465 (1996-07-01), Frye et al.
patent: 5631499 (1997-05-01), Hosomi et al.
patent: 5659201 (1997-08-01), Wollesen
patent: 5691248 (1997-11-01), Cronin et al.
patent: 5726502 (1998-03-01), Beddingfield
patent: 5792594 (1998-08-01), Brown et al.
patent: 5795818 (1998-08-01), Marrs
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5838067 (1998-11-01), Baek
patent: 5854513 (1998-12-01), Kim
patent: 5883435 (1999-03-01), Geffken et al.
patent: 5902686 (1999-05-01), Mis
patent: 6013571 (2000-01-01), Morrell
patent: 6022792 (2000-02-01), Ishii et al.
patent: 6077726 (2000-06-01), Mistry et al.
patent: 6107180 (2000-08-01), Munroe
patent: 6144100 (2000-11-01), Shen et al.
patent: 6177731 (2001-01-01), Ishida et al.
patent: 6181569 (2001-01-01), Chakravorty
patent: 6184143 (2001-02-01), Ohashi et al.
patent: 6187680 (2001-02-01), Costrini et al.
patent: 6229711 (2001-05-01), Yoneda
patent: 6251501 (2001-06-01), Higdon
patent: 6277669 (2001-08-01), Kung et al.
patent: 6287893 (2001-09-01), Elenius
patent: 6300250 (2001-10-01), Tsai
patent: 6359328 (2002-03-01), Dubin
patent: 6362087 (2002-03-01), Wang et al.
patent: 6375062 (2002-04-01), Higdon
patent: 6380061 (2002-04-01), Kobayashi
patent: 6426281 (2002-07-01), Lin et al.
patent: 6429120 (2002-08-01), Ahn et al.
patent: 6472745 (2002-10-01), Iizuka
patent: 6479900 (2002-11-01), Shinogi et al.
patent: 6570251 (2003-05-01), Akram
patent: 6605528 (2003-08-01), Lin
patent: 6613663 (2003-09-01), Furuya
patent: 6614091 (2003-09-01), Downey et al.
patent: 6639299 (2003-10-01), Aoki
patent: 6642136 (2003-11-01), Lee et al.
patent: 6646347 (2003-11-01), Mercado et al.
patent: 6653563 (2003-11-01), Bohr
patent: 6683380 (2004-01-01), Efland et al.
patent: 6706554 (2004-03-01), Ogura
patent: 6707124 (2004-03-01), Wachtler et al.
patent: 6707159 (2004-03-01), Kumamoto et al.
patent: 6756664 (2004-06-01), Yang
patent: 6762122 (2004-07-01), Mis et al.
patent: 6780748 (2004-08-01), Yamaguchi et al.
patent: 6791178 (2004-09-01), Yamaguchi et al.
patent: 6841872 (2005-01-01), Ha et al.
patent: 6853076 (2005-02-01), Datta et al.
patent: 6853078 (2005-02-01), Yamaya
patent: 6875681 (2005-04-01), Bohr
patent: 6940169 (2005-09-01), Jin et al.
patent: 6943440 (2005-09-01), Kim et al.
patent: 6959856 (2005-11-01), Oh et al.
patent: 6963136 (2005-11-01), Shinozaki et al.
patent: 6977435 (2005-12-01), Kim et al.
patent: 7045899 (2006-05-01), Yamane et al.
patent: 7078331 (2006-07-01), Kwon et al.
patent: 7078822 (2006-07-01), Dias et al.
patent: 7220657 (2007-05-01), Ihara et al.
patent: 7239028 (2007-07-01), Anzai
patent: 7465654 (2008-12-01), Chou et al.
patent: 7547969 (2009-06-01), Chou et al.
patent: 2001/0026954 (2001-10-01), Takao
patent: 2001/0040290 (2001-11-01), Sakurai et al.
patent: 2001/0051426 (2001-12-01), Pozder et al.
patent: 2002/0016079 (2002-02-01), Dykstra
patent: 2002/0043723 (2002-04-01), Shimizu et al.
patent: 2002/0079576 (2002-06-01), Seshan
patent: 2002/0100975 (2002-08-01), Kanda
patent: 2002/0158334 (2002-10-01), Vu et al.
patent: 2003/0006062 (2003-01-01), Stone et al.
patent: 2003/0008133 (2003-01-01), Paik
patent: 2003/0020163 (2003-01-01), Hung
patent: 2003/0052409 (2003-03-01), Matsuo
patent: 2003/0080416 (2003-05-01), Jorger
patent: 2003/0102551 (2003-06-01), Kikuchi
patent: 2003/0127730 (2003-07-01), Weng
patent: 2003/0127734 (2003-07-01), Lee et al.
patent: 2003/0162383 (2003-08-01), Yamaya
patent: 2003/0168733 (2003-09-01), Hashimoto
patent: 2003/0218246 (2003-11-01), Abe et al.
patent: 2003/0219966 (2003-11-01), Jin et al.
patent: 2003/0222295 (2003-12-01), Lin
patent: 2004/0007779 (2004-01-01), Arbuthnot et al.
patent: 2004/0009629 (2004-01-01), Ahn et al.
patent: 2004/0023450 (2004-02-01), Katagiri et al.
patent: 2004/0040855 (2004-03-01), Batinovich
patent: 2004/0048202 (2004-03-01), Lay
patent: 2004/0070042 (2004-04-01), Lee
patent: 2004/0130020 (2004-07-01), Kuwabara
patent: 2004/0145052 (2004-07-01), Ueno
patent: 2004/0166659 (2004-08-01), Lin
patent: 2004/0188839 (2004-09-01), Ohtsuka
patent: 2004/0253801 (2004-12-01), Lin
patent: 2005/0277283 (2005-12-01), Lin
patent: 2006/0019490 (2006-01-01), Chou
patent: 2006/0060961 (2006-03-01), Lin et al.
patent: 2006/0076678 (2006-04-01), Kim
patent: 2006/0091540 (2006-05-01), Chou
patent: 2008/0284037 (2008-11-01), Andry et al.
patent: 1536469 (2005-06-01), None
patent: 02-213147 (1990-08-01), None
patent: 10-275811 (1998-10-01), None
patent: 11-274200 (1999-10-01), None
patent: 11-354579 (1999-12-01), None
patent: 2000-036515 (2000-02-01), None
patent: 2000-183090 (2000-06-01), None
patent: 2000-228420 (2000-08-01), None
patent: 2000-228423 (2000-08-01), None
patent: 2003-031727 (2003-01-01), None
patent: 2003-229451 (2003-08-01), None
patent: 2004-193301 (2004-07-01), None
patent: 515016 (2002-12-01), None
patent: 419765 (2001-01-01), None
patent: 452930 (2001-09-01), None
patent: 483045 (2002-04-01), None
patent: 490803 (2002-06-01), None
patent: 498529 (2002-08-01), None
patent: 506025 (2002-10-01), None
patent: 511243 (2002-11-01), None
patent: 517334 (2003-01-01), None
patent: 518700 (2003-01-01), None
patent: 519707 (2003-02-01), None
Mistry, K. et al. “A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEEE International Electron Devices Meeting (2007) pp. 247-250.
Edelstein, D.C., “Advantages of Copper Interconnects,” Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference (1995) pp. 301-307.
Theng, C. et al. “An Automated Tool Deployment for ESD (Electro-Static-Discharge) Correct-by-Construction Strategy in 90 nm Process,” IEEE International Conference on Semiconductor Electronics (2004) pp. 61-67.
Gao, X. et al. “An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance,” Solid-State Electronics, 27 (2003), pp. 1105-1110.
Yeoh, A. et al. “Copper Die Bumps (First Level Interconnect) and Low-K 5 Dielectrics in 65nm High Volume Manufacturing,” Electronic Components and Technology Conference (2006), pp. 1611-1615.
Hu, C-K. et al. “Copper-Polyimide Wiring Technology for VLSI Circuits,” Materials Research Society Symposium Proceedings VLSI V (1990) pp. 369-373.
Roesch, W. et al. “Cycling copper flip chip interconnects,” Microelectronics Reliability, 44 (2004) pp. 1047-1054.
Lee, Y-H. et al. “Effect of ESD Layout on the Assembly Yield and Reliability,” International Electron Devices Meeting (2006) pp. 1-4.
Yeoh, T-S. “ESD Effects on Power Supply Clamps,” Proceedings of the 6th International Sympoisum on Physical & Failure Analysis of Integrated Circuits (1997) pp. 121-124.
Edelstein, D. et al. “Full Copper Wiring in a Sub-0.25 pm CMOS ULSI Technology,” Techn

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Chip structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chip structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip structure will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2736347

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.