Chip stack with active cooling system

Details Chip stack with active cooling system Chip stack with active cooling system

2000-06-15

2001-05-22

Picard, Leo P. (Department: 2835)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S704000, C361S749000, C361S719000, C174S016100, C174S252000, C174S254000

Reexamination Certificate

active

06236565

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
The present invention relates generally to chip stacks, and more particularly to a stackable integrated circuit chip package including a flex circuit and a carrier which allows multiple chip packages to be quickly, easily and inexpensively mechanically registered and interconnected or assembled into a chip stack having a minimal profile.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the “footprint” typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant's U.S. Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, U.S. Pat. No. 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and U.S. Pat. No. 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a chip stack which involves the use of stackable integrated circuit chip packages including flex circuits and carriers. The inclusion of the carriers in the chip packages of the present invention provides numerous advantages in the assembly of the chip stack, including significantly greater ease in achieving and maintaining the registry or alignment between the chip packages within the stack. Additionally, the use of the carriers significantly simplifies the interconnection or assembly of the chip packages into a chip stack. The carriers are further specifically adapted to maximize the flow of cooling air about the integrated circuit chips of the chip packages, with the chip stack constructed in accordance with the present invention preferably being used in combination with an active cooling system.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a stackable integrated circuit chip package which comprises a carrier and a flex circuit. The flex circuit itself comprises a flexible substrate having opposed top and bottom surfaces. Disposed on the substrate, and in particular the top surface thereof, is a conductive pattern. The substrate is wrapped about and attached to at least a portion of the carrier such that the conductive pattern defines first and second portions. Also included in the chip package is an integrated circuit chip which is electrically connected to the first portion of the conductive pattern such that an air path is defined between the integrated circuit chip and the carrier. The chip package is configured such that the second portion of the conductive pattern and the integrated circuit chip are each electrically connectable to another stackable integrated circuit chip package.
In the chip package of the present invention, the carrier is sized and configured to be releaseably attachable to the carrier of at least one other identically configured stackable integrated circuit chip package in a manner wherein the chip packages, when attached to each other, are maintained in registry along first and second axes which are generally co-planar and extend in generally perpendicular relation to each other. The carrier of the chip package has a generally rectangular top section which defines inner and outer surfaces and opposed pairs of longitudinal and lateral sides. In addition to the top section, the carrier includes a pair of identically configured side rail sections which extend along respective ones of the longitudinal sides of the top section and each define an outer surface and a distal edge. In the chip package, the bottom surface of the substrate is attached to portions of the outer surfaces of the top section and the side rail sections. Additionally, the substrate is wrapped about and attached to the carrier such that the first portion of the conductive pattern extends over portions of the outer surfaces of the side rail sections, with the second portion of the conductive pattern extending over a portion of the outer surface of the top section in spaced, generally parallel relation to the first portion. The substrate itself preferably has a generally rectangular configuration defining opposed pairs of longitudinal and lateral peripheral edge segments. The conductive pattern extends along the top surface of the substrate to the lateral peripheral edge segments thereof. The substrate is preferably sized relative to the carrier such that when the substrate is wrapped about portions of the outer surfaces of the top section and side rail sections, the lateral peripheral edge segments of the substrate extend to approximately respective ones of the distal edges of the side rail sections.
The integrated circuit chip of the chip package of the present invention is preferably a TSOP (thin small outline package) device comprising a body having opposed, generally planar top and bottom surfaces, an opposed pair of longitudinal sides, and an opposed pair of lateral sides. In addition to the body, the integrated circuit chip includes a plurality of conductive leads which protrude or extend from each of the longitudinal sides of the body. The conductive leads of the integrated circuit chip are electrically connected to the first portion of the conductive pattern. The chip package may further comprise a Z-axis pad which is electrically connected to the conductive leads for facilitating the electrical connection of the chip package to the second portion of the conductive pattern of another stackable integrated circuit chip package. As an alternative to the Z-axis pad, the chip package may comprise a support member which is electrically connected to the conductive leads for facilitating the electrical connection of the chip package to a mother board. The chip package including the support member as an alternative to the Z-axis pad provides a base chip package upon which other chip packages may be stacked to form a chip stack in accordance with the present invention. The conductive leads are also preferably sized and configured such that a top air path is defined between the top surface of the body and the inner surface of the top section, and a bottom air path is defin

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